Memory system having programmable control parameters

A memory system comprising:

• an array of memory cells arranged in a multiplicity of rows and a multiplicity of columns, with each cell located in one of the rows being coupled to a common word line and with each cell located in one of the columns being coupled to a common bit line;
• a memory controller, operably coupled to the array said memory controller configured to control memory operations, with the memory operations comprising programming operations to program the memory cells and reading operations to read the memory cells;
• a plurality of non-volatile data storage units, with the data storage units storing control parameter data used by the memory controller to control the memory operations;
• and
• modification circuitry, operably coupled to the data storage units, the modification circuitry configured to modify the control parameter data so as to alter the memory operations.

A memory system comprising:

• an array of memory cells arranged in a multiplicity of rows and columns;
• a memory controller, operably coupled to the array of memory cells, configured to control reading and programming operations on the array of memory cells, with the reading and programming operations being controlled in response to control parameters;
• a data storage structure, operably coupled to the memory controller, said data storage structure configured to store the control parameters;
• and
• switching mode circuitry configured to switch the memory system between a normal operating mode wherein the memory reading and programming operations can be carried out and an alternative operating mode wherein the control parameters stored in the data storage structure can be altered.

A flash memory system implemented in an integrated circuit, said memory system comprising:

• a plurality of memory terminals for providing an interface between the integrated circuit and an environment external to the integrated circuit;
• an array of flash memory cells arranged in a multiplicity of rows and columns;
• a memory controller, operably coupled to the array of flash memory cells, said memory controller configured to carry out memory programming, erasing and reading operations in response to a plurality of control parameters;
• a plurality of data storage units configured to store the control parameters;
• mode control circuitry configured to switch the memory system between a normal operating mode where the memory programming, erasing and reading operations can be carried out and an alternative operating mode where the control parameters can be altered by way of the memory terminals.

A method of controlling operation of a memory system having an array of memory cells arranged in a multiplicity of rows and columns, the method comprising the following steps:

• placing the memory system to an alternative operating mode:
• storing a plurality of control parameters in data storage units separate from the array of memory cells;
• switching the memory system from the alternative operating mode to a normal operating mode;
• and
• programming data into the array of memory cells using the stored control parameters.

A method of controlling operation of a memory system having an array of memory cells arranged into a multiplicity of rows and columns, said method comprising the following steps:

• applying control parameter data to terminals of the memory system;
• storing a plurality of control parameters in data storage units indicative of the applied control parameter data;
• programming data into the array of memory cells using the stored control parameters;
• reading data in the array of memory cells using the stored control parameters;
• and
• erasing data in the array using the stored control parameters.