US 5,801,547 A · Embedded memory for field programmable gate array

Abstract

A programmable logic device has a configuration memory which is partitioned so that it includes at least one subarray available through the programmable interconnect of the user configurable logic to be used as user memory. Subarrays of the configuration memory have independent access logic coupled with them, and coupled to the user logic array so that they may be used independently as user memories. Subarray memory access logic is provided for each subarray of memory elements, and connected to the logic cell array, and optionally to the plurality of input/output cells on the device, including a subarray decoder used for selecting addressed memory elements in the corresponding subarray in response to address signals and control signals supplied across the interconnect structures of the logic cell array, and a subarray I/O path used to provide input and output data signals between the interconnect structures of the logic cell array and addressed memory elements in the subarray. Thus, each subarray of memory elements, its corresponding subarray decoder and subarray I/O path, are independently configurable in the programmable logic device for use as user memory.

Drawings

Drawings are temporarily unavailable. Open the PDF at USPTO

Drawings

Claims17

Dependent claims

A programmable logic device, comprising:

a plurality of input/output cells;
a configurable logic array of configurable logic cells and interconnect structures;
a memory array of memory elements coupled with the configurable logic array such that memory elements in the memory array store data to program the configurable logic array, said memory array including a subarray of addressable memory elements coupled with a corresponding subarray of the configurable logic array;
memory access logic coupled with the memory array and the plurality of input/output cells, the memory access logic including address decode logic configurable to receive address signals from the plurality of input/output cells and memory data path logic configurable to receive data signals from and supply data signals to the plurality of input/output cells;
a subarray decoder coupled to the configurable logic array, the subarray decoder coupled to said subarray of the memory array and decoding address signals from the interconnect structures of the configurable logic array to address memory elements in said subarray;
and
a subarray I/O path coupled to the configurable logic array, the subarray I/O path coupled to said subarray of the memory array and providing input and output data signals between the interconnect structures of the configurable logic array and addressed memory elements in said subarray.

4 more elements

A programmable logic device, comprising:

a plurality of input/output cells;
a configurable logic array of configurable logic cells and interconnect structures;
a memory array of memory elements, coupled with the configurable logic array, such that memory elements in the memory array store data to program the configurable logic array, said memory array including a set, having more than one member, of subarrays of addressable memory elements, members of said set coupled with corresponding subarrays of the configurable logic array;
memory access logic coupled with the memory array and the plurality of input/output cells, the memory access logic including address decode logic configurable to receive address signals from the plurality of input/output cells, and memory data path logic configurable to receive data signals from and supply data signals to the plurality of input/output cells;
a plurality of subarray decoders and corresponding configurable interconnect circuits coupled to the configurable logic array, the subarray decoders programmably connectable by the corresponding configurable interconnect circuits to corresponding subarrays in said set of subarrays and decoding address signals from the interconnect structures of the configurable logic array to address memory elements in corresponding subarrays;
and
a plurality of subarray I/O path circuits and corresponding configurable interconnect circuits coupled to the configurable logic array, the subarray I/O path circuits programmably connectable by the corresponding configurable interconnect circuits to corresponding subarrays of said set of subarrays and providing input and output data signals between the interconnect structures of the configurable logic array and addressed memory elements in corresponding subarrays.

4 more elements

A programmable logic device, comprising:

a plurality of input/output cells;
a configurable logic array of configurable logic cells and interconnect structures coupled with the plurality of input/output cells;
a configuration memory, coupled with the configuration logic array and the plurality of input/output cells, such that the configuration memory stores data to program the configurable logic array, said configuration memory including a set, having more than one member, of subarrays of addressable static random access memory (SRAM) elements, members of said set coupled with corresponding subarrays of the configurable logic array and defining logic functions of corresponding subarrays of the configurable logic array;
global memory access logic coupled with the configuration memory and the plurality of input/output cells, the memory access logic including address decode logic configurable to receive address signals from the plurality of input/output cells and in response select addressed SRAM elements in the configuration memory, and memory data path logic configurable to receive data signals from the plurality of input/output cells and the configurable logic array for writing to addressed SRAM elements, and configurable to supply data signals read from addressed SRAM elements to the plurality of input/output cells and the configurable logic array;
a plurality of subarray decoders with corresponding configurable interconnect circuits coupled to the configurable logic array, the subarray decoders programmably connectable under control of the configuration memory by the corresponding configurable interconnect circuits to corresponding subarrays in said set of subarrays and decoding address signals from the interconnect structures of the configurable logic array to address SRAM elements in corresponding subarrays;
a plurality of subarray I/O path circuits and corresponding configurable interconnect circuits coupled to the configurable logic array, the subarray I/O path circuits programmably connectable by the corresponding configurable interconnect circuits to corresponding subarrays of said set of subarrays and providing input and output data signals between the interconnect structures of the configurable logic array and addressed SRAM elements in corresponding subarrays;
wherein the configurable interconnect circuits having corresponding subarray decoders include a programmable switch including inputs connected to the configurable logic array, and including outputs connected to the configurable logic array, and outputs connected to the subarray decoder for the corresponding subarray of the configuration memory;
and
wherein the configurable interconnect circuits having corresponding subarray I/O path circuits include a programmable switch
including inputs connected to the logic cell array and inputs connected to the data I/O path for the corresponding subarray of the configurable memory, and
including outputs connected to the logic cell array and outputs connected to said subarray I/O path circuit for the corresponding subarray of the configurable memory.

8 more elements

Dependencies are inferred from the claim text.

Description6,745 words

Summary2,320 words

#1. Field of the Invention

#The present invention relates to integrated circuits, and more particularly to field programable logic devices, such as field programmable gate arrays (FPGAs) having programble core logic, configuration memory for programming the core logic, logic for programming the configuration memory, and interfaces to external pads and pins.

#2. Description of Related Art

Brief description of the drawings6 figures

#FIG. 1 shows an FPGA chip and the relationships among external pads, the FPGA user logic structures and the configuration memory according to the prior art.

#FIG. 2 shows a structural relationship between a pad, a pad driver, a portion of FPGA core logic, and the FPGA configuration memory, showing a configuration memory subarray according to the present invention.

#FIG. 3 illustrates the layout of one example FPGA architecture in which the configuration memory is partitioned into a plurality of subarrays according to the present invention.

Detailed description4,279 words

#The detailed description of a preferred embodiment of the invention is illustrated with respect to FIGS. 2 through 6.

#FIG. 2 shows on structural relationship between pads 31, a programmable switch 34, the FPGA user configurable logic 39 (including interconnect resources not shown), and the configuration memory 38, according to the invention. Programmable switch 34 can access both the configuration memory 38 and the user logic 39. Programmable switch 34 can send and receive data to and from user logic 39 as indicated by the bidirectional bus 35 and can also send and receive data from configuration memory 38 as indicated by bidirectional bus 36. FIG. 2 illustrates that the underlying configuration memory 38 controls the pad drivers 33, the programmable switch 34 and the user logic 39. The configuration memory 38 also controls programmable interconnect points in the interconnect structure within the user logic of the FPGA (not shown in this diagram). The pads 31 and pad drivers 33 connect to programmable switch 34. Connections which programmable switch 34 can make include:

#1. apply an input signal from a pad 31 to a line of bus 35 to the FPGA user logic 39, thereby allowing a user to apply an input signal to the FPGA user logic;

Facts

Application

08/735,830Filed 23 Oct 1996

Priority

GB 96044961 Mar 1996

Granted

1 Sep 1998

Term ended

23 Oct 2016

Estimated · how

20 years from earliest known nonprovisional domestic filing. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination. Patent term adjustment is unavailable; no adjustment was added.

Classification4 codes

H03K 19/1776
Structural details of configuration resources: for memories
H03K 19/17736
Arranged in matrix form: structural details of routing resources
H03K 19/17744
Structural details of routing resources: for input/output signals
H03K
Pulse technique

Embedded memory for field programmable gate array

Life of this patent

Embedded memory for field programmable gate array

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims17

Description6,745 words

Drawings

Classification4 codes

Life of this patent

Description6,745 words