US 5,801,546 A · Interconnect architecture for field programmable gate array using variable length conductors

Abstract

An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.

Claims5

Dependent claims

An FPGA comprising:

a plurality of logic elements, each logic element receiving logic element input signals from a plurality of logic element input lines and providing a plurality of logic element output signals;
a plurality of output lines formed to propagate selected ones of the logic element output signals in a single direction, including at least a first output line and a second output line, said first output line being of a length sufficiently different from a length of said second output line as to extend past a different number of logic elements from said second output line;
and
for each output line,
a plurality of programmable interconnection points (PIPs) that may be programmed to apply one of said logic element output signals to said output line;
and
at least one programmable interconnection point (PIP) that may be programmed to apply a signal on said output line to one of said logic element input lines.

4 more elements

Dependencies are inferred from the claim text.

Interconnect architecture for field programmable gate array using variable length conductors

Life of this patent

Interconnect architecture for field programmable gate array using variable length conductors

Life of this patent

Abstract

Claims5