Image processing system with a buffer memory

A buffer memory control circuit comprising:

• a companding unit for reversibly compressing input data stored in a buffer memory into compressed data for storage in a compressed data memory;
• a buffer memory control unit for controlling an operation for writing data into the buffer memory and an operation for reading data from the buffer memory, said buffer memory control unit controlling the data reading and writing operations consecutively and asynchronously, a memory capacity of the buffer memory being determined to ensure continuous and complete reading operations and writing operations for data which is compressed at a predetermined compression ratio by the commanding unit the buffer memory control unit comprising
• detecting means for detecting memory areas from an empty state to a full state in the buffer memory;
• first comparing means for comparing a result of detection by said detecting means with 0, when the detect result is 0, said first comparing means producing an empty signal;
• and
• second comparing means for comparing the detection result with a maximum memory area that can be accommodated by said buffer memory, when the detection result is equal to the maximum memory area, said comparing means producing a full signal,
• wherein the memory capacity of said buffer memory is determined depending on a memory capacity of the compressed data memory, a lowest compression rate when said commanding unit compresses the input data, and a ratio of a transfer rate of transferring input data to the buffer memory to that of transferring data from said companding unit to the buffer memory.