Source-coupled logic with reference controlled inputs

An MOSFET, reference controlled, source-coupled logic circuit for connection between a first power bus and a second power bus having a substantially constant potential difference between the buses, the logic circuit comprising:

• (a) a pair of MOSFET input transistors each having a source and an output and connected in a source-coupled arrangement, a first one of the input transistors having a gate forming a logic circuit input and the other input transistor having a gate connected to an external bias circuit shared by other logic circuits;
• (b) first and second pull-up resistive circuit elements each connected between the output of a respective different one of the input transistors and the first power bus;
• (c) at least one output transistor connected as a source-follower, the output transistor having an input connected to the output of one of the input transistors and having an output forming a circuit output;
• (d) a transistor, for conveying a substantially constant current, connected between the coupled input transistor sources and the second power bus and having an input connected to said bias circuit shared by multiple logic circuits, the constant current being controlled by the bias circuit;
• and
• (e) an input buffer circuit connected to the logic circuit input and including a differential comparator circuit and a voltage shifting circuit for translating the logic voltage levels applied to the input buffer circuit to logic levels compatible with said logic circuit.

An MOSFET, reference controlled, source-coupled logic circuit for connection between a first power bus and a second power bus having a substantially constant potential difference between the buses, the logic circuit comprising:

• (a) a pair of MOSFET input transistors each having a source and an output and connected in a source-coupled arrangement, a first one of the input transistors having a gate forming a logic circuit input and the other input transistor having a gate connected to an external bias circuit shared by other logic circuits;
• (b) first and second pull-up resistive circuit elements each connected between the output of a respective different one of the input transistors and the first power bus;
• (c) at least one output transistor connected as a source-follower, the output transistor having an input connected to the output of one of the input transistors and having an output forming a circuit output;
• (d) a transistor, for conveying a substantially constant current, connected between the coupled input transistor sources and the second power bus and having an input connected to said bias circuit shared by multiple logic circuits, the constant current being controlled by the bias circuit;
• and
• (e) an output buffer circuit connected to the logic circuit output and including an SCL gate followed by a CMOS inverter for translating the logic voltage levels from the logic circuit output to other logic levels.