MOS-technology power device integrated structure and manufacturing process thereof

A process for manufacturing a MOS-technology power device integrated structure, comprising the steps of:

• forming a plurality of first regions of a first conductivity type and a frame region of the first conductivity type in a lightly doped semiconductor layer of a second conductivity type, the frame region surrounding and being merged with the plurality of first regions at each end of each first region;
• forming a source region of the second conductivity type in each first region;
• forming a plurality of first gate regions, each first gate region being formed over the semiconductor layer between adjacent first regions and extending over a lateral portion of each region;
• forming a plurality of gate metal fingers, each gate metal finger extending over and contacting a portion of a respective first gate region;
• and
• forming a source metal plate and source metal fingers extending from the source metal plate above the semiconductor layer, each source metal finger extending over and contacting at least a portion of a respective first region and the source region formed therein such that the gate metal fingers and the source metal fingers are interdigitated.

A process for manufacturing a MOS power device, comprising the steps of:

• a) forming an oxide layer over a lightly doped semiconductor layer of a second conductivity type;
• b) selectively removing the oxide layer to open windows in the oxide layer;
• c) implanting a heavy dose of a first dopant of a first conductivity type into the lightly doped semiconductor layer through the windows in the oxide layer;
• d) diffusing the first dopant within the lightly doped semiconductor layer to form a plurality of first regions, a plurality of second regions that are disposed in parallel with the plurality of first regions, and a frame region surrounding and merged with ends of each of the plurality of first regions and the plurality of second regions;
• e) removing the oxide layer;
• f) implanting a second dopant of the second conductivity type in the lightly doped semiconductor layer to form a plurality of regions of the second conductivity type, each region of the second conductivity type being formed between a first region and a second region, said second dopant being implanted in a dose suitable not to invert a conductivity type of the plurality of first regions, a conductivity type of the plurality of second regions and a conductivity type of the frame region;
• g) forming a thin oxide layer over the lightly doped semiconductor layer;
• h) forming a polysilicon layer over the thin oxide layer;
• i) selectively removing the polysilicon layer and the thin oxide layer to define a plurality of first gate regions, each first gate region being formed over the semiconductor layer between adjacent first regions and extending over a lateral portion of the adjacent first regions;
• j) implanting a low dose of a third dopant of the first conductivity type in each of the first regions to form lightly doped channel portions at the lateral portions of the first regions;
• k) selectively implanting a heavy dose of a fourth dopant of the second conductivity type in the first regions to form at least one source region;
• l) forming a dielectric layer over the lightly doped semiconductor layer and the polysilicon layer;
• m) selectively removing the dielectric layer to open contact windows respectively over the plurality of first regions and over the plurality of first gate regions;
• n) forming a metal layer over the dielectric layer;
• and
• o) selectively removing the metal layer to form a source metal plate, source metal fingers extending over and contacting the first regions and the at least one source region within the first region, and gate metal fingers extending over and contacting at least a potion of each first gate region.

A MOS-technology power device integrated structure comprising:

• a plurality of first regions of a first conductivity type formed in a semiconductor layer of a second conductivity type, each of said first regions including a source region of the second conductivity type;
• a frame region of the first conductivity type formed in the semiconductor layer surrounding and being merged with said plurality of first regions at each end of each said first region;
• a plurality of first gate regions, each first gate region extending over the semiconductor layer between respective adjacent first regions and extending over a lateral portion of each adjacent first region, said plurality of first gate regions extending from a gate frame region surrounding and merged with each end of said plurality of first gate regions;
• a plurality of gate metal fingers, each gate metal finger extending over and electrically connected to a portion of a respective first gate region;
• a plurality of source metal fingers, each source metal finger extending outwardly from a source pad disposed above the semiconductor layer, each source metal finger extending over a respective first region and contacting at least a portion of said first region and the respective source region within the at least a portion of the first region, so that the plurality of source metal fingers and the plurality of gate metal fingers are interdigitated;
• and
• at least one second gate region extending orthogonally to the plurality of first gate regions and having its ends merged with said gate frame region.

A process for manufacturing a MOS-technology power device integrated structure, comprising the steps of:

• forming a plurality of first regions of a first conductivity type and a frame region of the first conductivity type in a lightly doped semiconductor layer of a second conductivity type, the frame region surrounding and being merged with each end of the plurality of first regions;
• forming a source region of the second conductivity type in each of said plurality of first regions;
• forming over the semiconductor layer a gate metal frame;
• forming a plurality of first gate regions above the semiconductor layer, each first gate region extending between adjacent first regions and extending over a lateral portion of each adjacent first region;
• forming at least one second gate region above the semiconductor layer and extending orthogonally to said plurality of first gate regions, the at least one second gate region extending between opposite sides of said gate metal frame and having its ends merged with the gate metal frame, said plurality of first gate regions being merged at one end with said gate metal frame and at a second end with said at least one second gate region;
• forming a plurality of gate metal fingers, each one extending over and contacting a portion of a respective first gate region;
• and
• forming a source metal plate and source metal fingers extending from the source metal plate above the semiconductor layer, each source metal finger extending over and contacting at least a portion of a respective first region and the source region formed therein such that the gate metal fingers and the source metal fingers are interdigitated.

A process for manufacturing a MOS power device comprising the steps of:

• a) selectively implanting and diffusing a dopant of a first conductivity type into a lightly doped semiconductor layer of a second conductivity type to form a plurality of first regions and a plurality of third regions that are disposed in parallel with the plurality of first regions, at least one second region extending orthogonally to the plurality of first regions and the plurality of thirds regions, and a frame region surrounding and merged with each end of the plurality of first regions, each end of the plurality of third regions and each end of the at least one second region;
• b) implanting a dopant of the second conductivity type into the semiconductor layer to form a plurality of regions of the second conductivity type, each region of the second conductivity type being formed between a first region and a third region, said second dopant being implanted in a dose suitable not to invert a conductivity type of the plurality of first and third regions, a conductivity type of the frame region and a conductivity type of the at least one second region;
• c) forming a thin oxide layer above the semiconductor layer;
• d) forming a polysilicon layer over the thin oxide layer;
• e) selectively removing the polysilicon layer and the thin oxide layer to define a gate metal frame, a plurality of first gate regions and at least one second gate region, each first gate region being formed over the semiconductor layer between adjacent first regions and extending over a lateral portion of each first region, the second gate region being formed above the semiconductor layer and extending orthogonally to the first gate regions, the second gate region extending between opposite sides of the gate metal frame, the plurality of first gate regions having one end connected to the gate metal frame and a second end connected to the at least one second gate region;
• f) implanting a low dose of a third dopant of the first conductivity type in each of the first regions to form lightly doped channel portions at the lateral portions of the first regions;
• g) selectively implanting a heavy dose of a fourth dopant of the second conductivity type into the first regions to form at least one source region;
• h) forming a dielectric layer over the semiconductor layer and the polysilicon layer;
• i) selectively removing the dielectric layer to open contact windows over the plurality of first regions and over the plurality of first gate regions;
• l) forming a metal layer over the dielectric layer;
• m) selectively removing the metal layer to form a source metal plate, source metal fingers extending over and contacting a portion of the first regions and the source region within the portion of the first region, and gate metal fingers extending over and contacting a portion of each first gate region.