Data processor having an address translation buffer operable with variable page sizes

A data processor for supporting a virtual memory function in which a logical address space is divided into a plurality of virtual pages and a logical address is translated to a physical address at the page unit, comprising:

• a set associative type cache memory having a plurality of banks each having a plurality of memory fields each of which includes a virtual page number for indicating a virtual page and a physical page number corresponding to the virtual pare number;
• means for providing a control signal;
• and
• an index address generating circuit which receives at least a portion of the logical address and the control signal, wherein the index address generating circuit generates an index address for selecting a memory field from each of the plurality of banks, and wherein the index address generating circuit generates a different index address in accordance with the control signal.

A data processor for supporting a virtual memory function in which a logical address space is divided into a plurality of virtual pages and a logical address from the central processing unit is translated to a physical address at the page unit, comprising:

• a set associative type cache memory having a plurality of banks each having a plurality of memory fields each of which includes a virtual page number for indicating a virtual page and a physical page number corresponding to the virtual page number;
• a circuit designating one of the plurality of banks, which includes a memory field having information to be replaced according to a predetermined rule;
• and
• a central processing unit coupled to the circuit and changing the designation of said bank by said circuit in response to the central processing unit executing predetermined software.

A data processor having a virtual memory function in which a logical address space is divided into a plurality of virtual pages, a logical address is translated to a physical address at the virtual page unit, and a plurality of processes are executed using the virtual memory function, comprising:

• a multiple virtual mode in which the logical address is modified according to a process to be executed and each of said plurality of processes is capable of using an address over the logical address space;
• a single virtual mode in which said logical address is unmodified according to a process to be executed, wherein each of the plurality of processes is capable of using an address in an address space assigned thereto within the logical address space and a portion of said logical address space is exclusively assigned among the plurality of processes to be executed;
• and
• a selector selecting either said multiple virtual mode or said single virtual mode.

A data processor having a virtual memory function in which a logical address space of a central processing unit is divided into a plurality of virtual pages, a logical address is translated to a physical address at the virtual page unit, and a plurality of processes are executed using the virtual memory function, comprising:

• mode information designating an operation mode of the central processing unit, wherein the central processing unit operates in either a privileged mode or a user mode;
• control information designating a virtual memory mode which is either a multiple virtual mode or a single virtual mode in which each of said plurality of processes is capable of using an address over the logical address space in the multiple virtual mode and a logical address is modified according to a process using the logical address, and in which each of the plurality of processes is exclusively assigned portions of the logical address space in the single virtual mode and each of the plurality of processes is capable of using an address in an address portion assigned thereto without modifying the address by the process;
• a translation lookaside buffer accessed by using at least a portion of the logical address as an index address, and having a plurality of fields each of which includes process information for representing a process, a virtual page information representing a virtual page corresponding to said process, physical page information corresponding to the virtual page information, and share information indicating whether or not the virtual page corresponding to said process is shared with another process;
• and
• a control circuit for said translation lookaside buffer, wherein the control circuit uses the process information in a hit decision of the translation lookaside buffer if said share information designates a non-share condition, and wherein the control circuit uses said process information as memory protection information if said mode information represents the user mode of the central processing unit, the control information represents the single virtual mode and said share information represents the non-share condition.

A data processor having a virtual memory function in which a logical address space is divided into a plurality of virtual pages and a logical address is translated at the page unit to a physical address, comprising:

• a processing unit generating the logical address which includes an index address, a comparison address and an offset address;
• and
• a translation lookaside buffer translating the logical address generated by said processing unit to a physical address,
• wherein said translation lookaside buffer includes:
• a plurality of banks each having a plurality of entries each of which includes a virtual page number indicating a virtual page, size information indicating a size of said virtual page, and a physical page number corresponding to said virtual page number;
• a selector selecting an entry designated by said index address from each of said plurality of banks in response to said index address;
• and
• a comparator comparing the virtual page number from the selected entry with said comparison address, wherein a bit number of the virtual page number to be compared is decided by the size information in the selected entry, and
• wherein said physical address is generated from said physical page number in said selected entry and said offset address.

A data processor having a virtual memory function in which a logical address space is divided into a plurality of virtual pages and a logical address is translated at the page unit to a physical address, and which executes a plurality of processes under the virtual memory function, comprising:

• a processing unit generating the logical address which comprises an index address, a comparison address and an offset address;
• a circuit outputting a process number to specify a process among the plurality of processes;
• a circuit settable by said processing unit and outputting index information for specifying an index;
• a translation lookaside buffer which translates the logical address generated by said processing unit to a physical address, and which includes:
• a plurality of banks each having a plurality of entries each of which includes a virtual page number for indicating a virtual page, and a physical page number corresponding to said virtual page number;
• a selector which selects either said index address in the logical address or an index address which is obtained by modifying said index address in the logical address by said process number, in accordance with said index information, and which selects an entry designated by the selected index address from each of said plurality of banks;
• and
• a comparator comparing a virtual page number from the selected entry with said comparison address,
• wherein said physical address is generated from said physical page number in said entry and said offset address.

A data processor having a virtual memory function in which a logical address space is divided into a plurality of virtual pages and a logical address is translated at the page unit to a physical address, comprising:

• a processing unit for generating the logical address which comprises an index address, a comparison address and an offset address;
• a bank designating circuit settable by said processing unit;
• a translation lookaside buffer which translates said logical address generated by said processing unit a physical address, and which includes:
• a plurality of banks each having a plurality of entries each of which comprises a virtual page number for representing the virtual page, and a physical page number corresponding to said virtual page number;
• a selector selecting an entry designated by said index address from each of said plurality of banks in response to said index address;
• a comparator comparing a virtual page number from the selected entry with said comparison address;
• and
• a bank selector designating a bank which is designated by said bank designation circuit to execute a replacement of an entry if said comparator indicates that a virtual page number corresponding to said comparison address is not stored in the selected entry,
• wherein said physical address is generated from said physical page number in said entry and said offset address.

A data processor having a virtual memory function in which a logical address space is divided into a plurality of virtual pages and a logical address is translated at the page unit to a physical address, and which executes a plurality of processes, comprising:

• a processing unit for generating the logical address having an index address, a comparison address and an offset address;
• a register settable with a process number for specifying a process among the plurality of processes by the processing unit;
• and
• a translation lookaside buffer which translates the logical address generated by said processing unit to a physical address and which includes:
• a plurality of entries each of which stores a virtual page number for representing the virtual page, a physical page number corresponding to said virtual page number, a process number for specifying a process, and common information indicating whether or not the virtual page represented by said virtual page number is shared among processes;
• a selector selecting an entry designated by said index address;
• and
• a comparator which compares a virtual page number from the selected entry with said comparison address, wherein it is determined by the common information whether or not a comparison between the process number stored in said register and the process number in the selected entry by the comparator is executed,
• wherein said physical address is generated from said physical page number in said entry and said offset address.