Phase error detecting method and phase tracking loop circuit

A phase error detecting method in a demodulation device for demodulating a phase-modulated signal, comprising the steps of:

• (a) recovering a signal by digitally filtering a transmitted phase-modulated signal to produce a recovered signal;
• (b) multiplying a phase difference information included in the recovered signal by a weight value according to a predetermined weighting function to generate weighted phase difference information;
• (c) deciding a transmitted phase information of said phase modulated signal to be one of predetermined reference phase values which is closest to said weighted phase difference information, thereby producing a decided phase information;
• and
• (d) correcting the phase of the recovered signal by the phase difference between said weighted phase difference information and the decided phase information.

A phase tracking loop in a communication device of a digital VSB modulation system, comprising:

• means for recovering Q-channel data by digital-filtering transmitted I-channel data;
• means for correcting the phases of said I-channel data and said Q-channel data by a predetermined weighted phase error value, to produce phase-corrected I-channel data and phase-corrected Q-channel data;
• means for estimating an I-channel level value closest to the phase-corrected I-channel data among predetermined reference I-channel level values, to produce an estimated I-channel level value;
• and
• means for detecting the difference between said phase-corrected I-channel data and said estimated I-channel level value, multiplying said difference by the sign of said phase-corrected Q-channel data to produce a phase error value, applying a weight according to a predetermined weighting function to said phase error value and feeding back said weighted phase error value to said means for correcting the phases.

A phase tracking loop in a communication device of a digital VSB modulation system, comprising:

• digital-filtering means for reconstructing first Q-channel data by filtering transmitted I-channel data;
• delay means for delaying said I-channel data for a filtering time of said digital-filtering means to output the delayed I-channel data as first I-channel data;
• first multiplying means for complex-multiplying said first I-channel data and said first Q-channel data by predetermined sine and cosine values, respectively, and outputting the multiplied values as second I-channel data and second Q-channel data, respectively;
• second multiplying means for multiplying said second I-channel data by a predetermined accumulation limiting value;
• estimating means for receiving said second Q-channel data and output of said second multiplying means, and estimating an I-level value closest to said second I-channel data in response to a predetermined residual phase error, to produce an estimated I-level value;
• phase error deciding means for receiving the estimated I-level value, second I-channel data, and said second Q-channel data, and applying a weight value according to a predetermined weighting function to the difference between said second I-channel data and said estimated I-level value, depending on the directionality of said second Q-channel data, to produce as an output a phase error value;
• dividing means for dividing the phase error value output from said phase error deciding means by a predetermined value and outputting said divided phase error value;
• accumulating means for accumulating said divided phase error value output from said dividing means;
• sine and cosine table storing means for outputting previously stored sine and cosine values to said first multiplying means based upon accumulated phase error values in said accumulating means;
• and
• accumulation limiting means for receiving said estimated I-level value and said second I-channel data, and subtracting said estimated I-level value from said second I-channel data, to output the difference as an accumulation limiting value to said second multiplying means.