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AssigneeInternational Business Machines Corporation
InventorDavid Stephen Levitan
Estimating the term…
A Content Addressable Memory (CAM) includes a plurality of conventional CAM cells arranged in rows and columns, the CAM cells being coupled together by word lines and bit lines for reading from and writing information into the CAM cells. Each CAM cell in a row is connected to a match line which provides an indication when an input word on the bit lines matches the contents of the cells coupled to the match line. A combinatorial logic circuit including a parity generator is coupled to the word lines and provides an indication when multiple words have been selected by an input word. The combinatorial logic circuit includes an OR circuit providing a first input to an AND circuit and a parity generator providing a second input to the AND which only provides an output when multiple word lines have been selected by an input word.
A self-checking content addressable memory for detecting multiple selected word lines comprising:
In a self-checking content addressable memory comprising an array of content addressable memory cells in "m" rows and "n" columns where "m" and "n" are any non-zero integer and means coupled to the columns as bit lines for writing information into and reading information from the content addressable memory cells in a selected row as a word line in a "write" and "read" operations, respectively, a method for detecting multiple selected word lines in a "read" operation, comprising the steps of:
Dependencies are inferred from the claim text.