US 5,796,413 AGranted

Graphics controller utilizing video memory to provide macro command capability and enhanched command buffering

AssigneeCompaq Computer Corporation

InventorsRonald Anthony Shipp, Stuart Hecht, Patrick Allen Harkin

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Abstract

An apparatus and method are disclosed for buffering graphics commands in a video graphics system, and for implementing graphics macro commands. The invention makes use of off-screen portions of video memory to create a dynamic command FIFO for commands, and to store command sequences for later or repeated use ("macros"). A command FIFO controller is provided, along with an on-chip bus FIFO and an on-chip command buffer (which is also a FIFO). Several multiplexers are also provided, so as to enable the command FIFO controller to create several different paths for commands coming into the graphics controller. Incoming commands may be routed to the command execution circuitry in several different ways: through the bus FIFO and command buffer to the command execution circuitry, directly to the command execution circuitry by bypassing the bus FIFO and command buffer, or from the bus FIFO into video memory to be stored in a dynamic command FIFO and later retrieved and sent into the command buffer. The command FIFO controller is also provided with macro address generation logic for providing read pointers to macros stored in video memory, read and write address generation logic for accessing the dynamic command FIFO stored in video memory, status generation logic for use in controlling the dynamic command FIFO, and busy status logic for use in software synchronization

Claims22

Dependent claims

For use in a computer graphics system comprising a bus interface;

a video memory;
a video memory controller circuitry having a memory controller address input for receiving addresses corresponding to locations within said video memory, a memory controller data input for receiving data to be written to said video memory, and a memory controller data output for outputting data read from said video memory;
a decoder circuitry having a decoder input, a decoder address output and a decoder data output, said decoder address output and said decoder data output responsive to graphics commands presented to said decoder input;
a first command path over which commands are transferrable from said bus interface to said decoder input;
a first address path over which addresses are transferrable from said decoder address output to said memory controller address input;
and a data path over which data are transferrable from said decoder data output to said memory controller data input;
the improvement comprising circuitry for implementing a graphics command buffer using a portion of said video memory, said circuitry for implementing a graphics command buffer comprising:
FIFO address generation circuitry for generating read and write addresses corresponding to locations within said video memory that will be used for implementing the graphics command buffer, said FIFO address generation circuitry having a FIFO address output;
a second address path over which addresses are transferrable from said FIFO address output to said memory controller address input;
a second command path over which commands are transferrable from said memory controller output to said decoder input;
a node dividing said first command path into first and second portions, said first portion being between said bus interface and said node, and said second portion being between said node and said decoder input;
and
a third command path over which commands are transferrable from said node to said memory controller data input.

10 more elements

A computer graphics system comprising:

a bus interface;
a video memory communicating with said bus interface;
a video memory controller circuitry having a memory controller address input for receiving addresses corresponding to locations within said video memory;
a memory controller data input for receiving data to be written to said video memory;
a memory controller data output for outputting data read from said video memory;
decoder circuitry having a decoder input, a decoder address output and a decoder data output, said decoder address output and said decoder data output responsive to graphics commands presented to said decoder input;
a first command path over which commands are transferrable from said bus interface to said decoder input;
a first address path over which addresses are transferrable from said decoder address output to said memory controller address input;
a data path over which data are transferrable from said decoder data output to said memory controller data input;
and
circuitry for implementing a graphics command buffer using a portion of said video memory, said circuitry for implementing a graphics command buffer comprising:
FIFO address generation circuitry for generating read and write addresses corresponding to locations within said video memory that will be used for implementing the graphics command buffer, said FIFO address generation circuitry having a FIFO address output;
a second address path over which addresses are transferrable from said FIFO address output to said memory controller address input;
a second command path over which commands are transferrable from said memory controller output to said decoder input;
a node dividing said first command path into first and second portions, said first portion being between said bus interface and said node, and said second portion being between said node and said decoder input;
and
a third command path over which commands are transferrable from said node to said memory controller data input.

14 more elements

Dependencies are inferred from the claim text.