US 5,796,127 AGranted

High electron mobility transistor

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsNorio Hayafuji, Yoshitsugu Yamamoto, Hirotaka Kizuki

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Abstract

A method of fabricating a semiconductor device includes forming a first mixed crystal semiconductor layer of AlAs and InAs; applying a solution containing a material easily combining with fluorine to the surface of the first mixed crystal semiconductor layer exposed to the atmosphere so that the material combines with fluorine that sticks to the surface of the first mixed crystal semiconductor layer; and annealing the first mixed crystal semiconductor layer in a vacuum. In this method, since the fluorine on the surface of the first mixed crystal semiconductor layer exposed to the atmosphere combines with the material included in the solution and is removed together with the material, a first mixed crystal semiconductor layer having no fluorine is produced. Therefore, unwanted infiltration of fluorine into the first mixed crystal semiconductor layer is avoided, resulting in a highly reliable semiconductor device with desired characteristics.

Claims4

Dependent claims

A semiconductor device comprising:

a compound semiconductor substrate;
an undoped channel layer disposed on the substrate;
an electron supply layer disposed on the channel layer, the electron supply layer comprising a mixed crystal semiconductor material comprising AlAs and InAs and, having a high concentration of a dopant impurity producing n type conductivity, and free of fluorine;
a Schottky barrier formation layer disposed on the electric supply layer, the Schottky barrier formation layer comprising an undoped mixed crystal semiconductor material comprising AlAs and InAs and free of fluorine;
an ohmic contact layer disposed on the Schottky barrier formation layer and having a high concentration of a dopant impurity producing n type conductivity;
a source electrode and a drain electrode on the ohmic contact layer;
a gate electrode disposed on a portion of the Schottky barrier formation layer between the source electrode and the drain electrode;
and
a protective film disposed on a portion of the Schottky barrier formation layer adjacent to the gate electrode and between the source electrode and the drain electrode.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/915,791Filed 21 Aug 1997 · continuation
Priority: JP 7-29811716 Nov 1995
Granted: 18 Aug 1998
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 30/015
Manufacture or treatment: of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
H10P 14/60
Formation of materials, e.g. in the shape of layers or pillars: of insulating materials
H10P 95/904
Thermal treatments, e.g. annealing or sintering: of Group III-V semiconductors
H10W 74/141
The semiconductor body being only partially enclosed: the encapsulations being on at least the sidewalls of the semiconductor body