Brake failure monitoring system

The brake monitoring system of claim wherein said latching circuit comprises:

• a voltage divider network connected between ground and a voltage rail, comprising a first resistor and a second resistor connected together in series, where said first resistor has a low resistance compared to said second resistor, and a DC isolating capacitor at the common point between the resistors to isolate the common point from ground;
• wherein each said signal producing sensor mechanism comprises a normally closed switch connected between ground and a second end of said first resistor opposite said common point;
• a first NAND gate having a first input connected through a normally open reset switch to ground and through a third resistor to said voltage rail, a second input, and an output;
• a second NAND gate having a first input connected to said output of said first NAND gate, a second input connected through an inverter to said common point of said resistors, and an output connected to said second input of said first NAND gate;
• an indicator means connected to said output of said second NAND gate;
• wherein, in an initial power-on state, each said signal producing sensor mechanism is closed so as to cause current flow through said voltage divider network, which current flow produces a low voltage at said common point compared to the voltage at said voltage rail, and a corresponding binary zero input at said inverter, and a corresponding binary one input at said second input of said second NAND gate so as to produce a binary one output from said second NAND gate;
• wherein said reset switch is open in an initial power-on state, so that said first input of said first NAND gate is at the voltage of said voltage rail, and is a binary one, and the second input of said first NAND gate is a binary one so as to produce a binary zero output from said first NAND gate;
• and accordingly, said first input of said second NAND gate is a binary zero, thus producing a stable binary one output from said second NAND gate;
• wherein, in a reset state, said first input of said first NAND gate is grounded through said reset switch so as to be a binary zero, and so as to produce a binary one output;
• and accordingly said first input of said second NAND gate is a binary one, thus producing a binary zero output from said second NAND gate, corresponding to said brake monitoring system being reset to a null output, and a binary zero at the second input of said first NAND gate;
• wherein, in a non-alarm state, said first input of said first NAND gate is removed from ground so as to be a binary one so as to still produce a binary one output, corresponding to said brake monitoring system having a null output;
• wherein, when an alarm state occurs, said threshold signal is produced as at least one signal producing sensor mechanism becomes open so as to cease current flow through said voltage divider network, whereby the voltage of said voltage rail appears at said common point and a binary one input, which is made to said inverter;
• wherein said binary one input to said inverter is indicative that said threshold signal is now present;
• wherein a corresponding binary zero output from said inverter appears at said second input of said second NAND gate so as to produce a binary one output that activates the respective indicator means;
• wherein said second input to said first NAND gate is also a binary one so as to produce a binary zero output therefrom;
• and accordingly said first input to said second NAND gate becomes a binary zero, thereby producing a stable binary one output therefrom;
• and
• wherein, after the onset of said alarm state but before a reset state, but in a circumstance when said signal producing sensor mechanism reverts to being closed, there is again current flow through said voltage divider network, a corresponding binary zero input at said inverter, and a corresponding binary one input into said second input of said second NAND gate, but said first input of said second NAND gate is at a binary zero, and accordingly said output from said second NAND gate remains at a binary one, thus keeping the respective indicator means activated, until said reset switch is closed.