Disk meshing and flexible storage mapping with enhanced flexible caching

A data processing system comprising:

• a processor that operates on various data, said processor comprising a processor memory, means for specifying a source address that identifies a requested data block located within another memory to be accessed by said processor, and means for requesting allocation of memory space in order to hold a specified data string, said data string having a length that requires a storage space of a specified plurality of data blocks;
• memory allocation means for allocating blocks of memory space for said specified plurality of data blocks, and for assigning source addresses to each of the allocated blocks of memory, the assigned source addresses comprising a series of adjacent addresses when possible;
• a hierarchical memory means comprising a cache and a long-term storage which has several independent sub-memories;
• and
• a storage control processor comprising pre-fetch means for making data blocks available within said cache for future access by said processor, said pre-fetch means comprising physical pre-read means, responsive to a request made by said processor for access to a specified data block identified by a specified source address, for performing a physical read on a per-block basis per I/O request from said long-term storage of selected adjacently addressed data blocks based on a current I/0 request from the processor and the contents of the cache, said selected adjacently addressed data blocks identified by a source address adjacent to said specified source address being stored in separate sub-memories of said several independent sub-memories different than a specified sub-memory of said sub-memories where said specified source address is stored.

A data processing system comprising:

• a host computer that operates on various data, said host computer comprising a processor memory and means for specifying, according to a source addressing scheme, a source address of a source block that corresponds to a requested data block located within another memory to be accessed by said host computer;
• and
• an external memory for storing data within target blocks according to a target addressing scheme;
• said storage controller comprising:
• address mapping means for correlating source addresses specified by said processor with target addresses that correspond to storage locations within said another memory, wherein said address mapping means comprises meshing means for distributing a set of adjacent source addresses on a per-block basis per I/O request to a plurality of sub-memories, and for assigning adjacent source addresses within said set of adjacent source addresses to different ones of said plurality of sub-memories;
• and
• configuration means for defining several parameters of said address mapping means based upon the physical storage characteristics of said external memory, to thereby configure said address mapping means to correlate source addresses of source blocks specified by said host computer with target addresses of target blocks that correspond to storage locations within said external memory.

A data processing system comprising:

• a host processor, said host processor specifying at least one of a plurality of adjacent source addresses identifying at least one requested data block located within a memory to be accessed by said processor, said host processor requesting allocation of storage space in a first memory to store a data string if said at least one requested data block is not present in said first memory;
• and
• a memory subsystem, said memory subsystem comprising an I/O processor for allocating blocks of memory to store said data string in said first memory and for mapping source addresses to target addresses, a hierarchical memory system, a subsystem control, and an I/O device manager, said hierarchical memory comprising said first memory connected by said subsystem control to a second memory, said second memory comprising a plurality of sub-memories and connected to said I/O device manager,
• wherein said I/O processor distributes each of said plurality of adjacent source addresses on a per-block basis per I/O request to one of said plurality of sub-memories on a rotating basis, and wherein no other adjacent source-addressed data block of said plurality of adjacent source addresses being distributed is assigned by said I/O processor to said one of said plurality of submemories.