US 5,790,614 AGranted

Synchronized clock using a non-pullable reference oscillator

AssigneeAlcatel Network Systems, Inc.

InventorWilliam E. Powell

Life of this patent

Estimating the term…

Loading patent…

Abstract

Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-locked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency jitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual jitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.

Claims4

Dependent claims

A method comprising the steps of:

comparing (14) a phase of a digital input signal (12) to a phase of a feedback output signal (16) for providing an error signal (18);
lowpass filtering (20) the error signal (18) for providing a filtered error signal (36);
providing a stable reference frequency signal (40);
and
frequency synthesizing (38) the feedback output signal (16) in response to the filtered error signal (36) and the stable reference signal (40):
wherein the step of frequency synthesizing comprises the steps of:
comparing (74) a phase of the stable reference signal (40) to a phase of a second feedback signal (76) for providing a second phase error signal (78);
comparing (98) the second phase error signal (78) to a phase accumulation modulation signal (96) for providing a reduced phase error signal (81);
filtering (82) the reduced phase error signal (81) for providing a filtered, reduced phase error signal (83);
providing (84) feedback the output signal (16) with a frequency that varies in proportion to the filtered, reduced phase error signal (83);
and
dividing (86) the output signal (16) by N, or by N+1 in response to a carry signal (88), for providing the second feedback signal (76).

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/675,649Filed 2 Jul 1996 · division
Priority: 9 Jun 1993
Granted: 4 Aug 1998
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H03L 7/1978
Using a phase accumulator for controlling the counter or frequency divider: using a cycle or pulse removing circuit
H03L 7/0994
The oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider: comprising an accumulator
H03L 7/1806
Using a frequency divider or counter in the loop: the frequency divider comprising a phase accumulator generating the frequency divided signal
H03L 7/235
With pulse counters or frequency dividers: nested phase locked loops