Back to results
US 5,790,539 AGranted
ASIC chip for implementing a scaleable multicast ATM switch
OwnerHung-Hsiang Jonathan Chao, Necdet Uzuninventors
Life of this patent
Estimating the term…
Abstract
An application specific integrated circuit (or "ASIC") chip for building a scaleable, multicast, asynchronous transfer mode (or "ATM") switch having on the order of 100 to a few thousand input and output ports. The ATM switch has a regular structure and may be easily expanded. Furthermore, the ATM switch permits synchronization for data and clock signals to be relaxed. Moreover, the switch system may be built using economic CMOS technology. The switch fabric of the ASIC chip can handle high line rates, supports multicasing functionality, and permits output groups to be flexibly altered. The ASIC chips may be arranged in an array thereby permitted the switch size to be scaled.
Claims25
A circuit for facilitating the routing, sorting, and grouping of cells, each cell including address and priority information, the circuit comprising:
- a) a first group of inputs for receiving a first group of input cells;
- b) a second group of inputs for receiving a second group of input cells;
- c) timing signal inputs for receiving a switch set timing signal, an address timing signal, and a priority timing signal;
- d) a mode input for receiving a mode signal;
- e) a clock signal input for receiving a clock signal;
- f) a group of outputs for providing a group of output cells;
- g) a first timing output for providing a first delayed address timing signal and a first delayed priority timing signal;
- h) a second timing output for providing a second delayed address timing signal;
- i) a plurality, N, of switch element arrays, each of the N switch element arrays having
- i) a first group of inputs for receiving a first group of M input cells,
- ii) a second group of inputs, coupled with M/N of the second group of inputs of the circuit, for receiving a second group of M/N input cells,
- iii) an address timing input for receiving an address timing signal,
- iv) a priority timing input for receiving a priority timing signal,
- v) a first group of outputs for providing a first group of M output cells,
- vi) a second group of outputs, coupled with M/N of the group of outputs of the circuit, for providing a second group of M/N output cells,
- vii) a first address output, coupled with the first timing output of the circuit, for providing a first delayed address timing signal,
- viii) a first priority output, coupled with the first timing output of the circuit, for providing a first delayed priority timing signal,
- ix) a second address output for providing a second delayed address timing signal, and
- x) a second priority output for providing a second delayed priority timing signal;
- and
- j) a plurality, N-1, of multiplexers arranged between adjacent ones of the N switch element arrays, each one of the N-1 multiplexers having
- i) a mode input, coupled with the mode input of the circuit, for receiving a multicast/unicast mode signal which is a portion of the mode signal received by the mode input of the circuit,
- ii) a control input for receiving a control signal corresponding to the particular multiplexer, wherein the control signal is derived from the mode signal provided to the mode input port of the circuit,
- iii) a first address timing input for receiving a first candidate address timing signal,
- iv) a second address timing input, coupled with the second address output of a preceding switch element array, for receiving a second candidate address timing signal,
- v) a first priority input, coupled with the timing signal inputs, for receiving a first candidate priority timing signal,
- vi) a second priority input, coupled with the second priority output of the preceding switch element array, for receiving a second candidate priority timing signal,
- vii) a first group of inputs, coupled with the first group of inputs of the circuit, for receiving a first group of candidate input cells,
- viii) a second group of inputs, coupled with the first group of outputs of the preceding switch element array, for receiving a second group of candidate input cells,
- ix) a mux output, coupled with the first address timing input of a next multiplexer, for providing a mux address timing signal,
- x) an address output, coupled with the address timing input of a next switch element array, for providing an address timing signal,
- xi) a priority output, coupled with the priority timing input of the next switch element array, for providing a priority timing signal, and
- xii) a group of outputs, coupled with the first group of inputs of the next switch element array, for providing a group of output cells.
30 more elements
A circuit receiving cells and a mode control signal, for facilitating the routing, sorting, and grouping of the cells, each cell including address and priority information, the circuit comprising:
- a) a plurality of switch element arrays for routing and sorting the cells based on the address and priority information to provide routed and sorted cells;
- and
- b) selective devices, arranged between each of the plurality of switch element arrays, for passing an appropriate one of the routed and sorted cells provided by a preceding one of the plurality of switch element arrays and cells received by the circuit, to a next of the plurality of switch element arrays based on the mode control signal.
A multicast grouping network comprising R rows of S columns of circuits, each of the r.times.s circuits receiving cells and a mode control signal, facilitating the routing, sorting, and grouping of the cells, each cell including address and priority information, and comprising:
- a) a plurality of switch element arrays for routing and sorting the cells based on the address and priority information to provide routed and sorted cells;
- and
- b) selective devices, arranged between each of the plurality of switch element arrays, for passing an appropriate one of the routed and sorted cells provided by a preceding one of the plurality of switch element arrays and cells received by the circuit, to a next of the plurality of switch element arrays based on the mode control signal,
- wherein, in each of the S columns, the routed and sorted cells provided by the plurality of switch element arrays of a circuit, are coupled with an input group of a lower adjacent circuit.
1 more element
A multicast grouping network comprising R rows of S columns of circuits for facilitating the routing, sorting, and grouping of cells, each cell including address and priority information, each of the R times S circuits comprising:
- a) a first group of inputs for receiving a first group of input cells;
- b) a second group of inputs for receiving a second group of input cells;
- c) timing signal inputs for receiving a switch set timing signal, an address timing signal, and a priority timing signal;
- d) a mode input for receiving a mode signal;
- e) a clock signal input for receiving a clock signal;
- f) a group of outputs for providing a group of output cells;
- g) a first timing output for providing a first delayed address timing signal and a first delayed priority timing signal;
- h) a second timing output for providing a second delayed address timing signal;
- i) a plurality, N, of switch element arrays, each of the N switch element arrays having
- i) a first group of inputs for receiving a first group of M input cells,
- ii) a second group of inputs, coupled with M/N of the second group of inputs of the circuit, for receiving a second group of M/N input cells,
- iii) an address timing input for receiving an address timing signal,
- iv) a priority timing input for receiving a priority timing signal,
- v) a first group of outputs for providing a first group of M output cells,
- vi) a second group of outputs, coupled with M/N of the group of outputs of the circuit, for providing a second group of M/N output cells,
- vii) a first address output, coupled with the first timing output of the circuit, for providing a first delayed address timing signal,
- viii) a first priority output, coupled with the first timing output of the circuit, for providing a first delayed priority timing signal,
- ix) a second address output for providing a second delayed address timing signal, and
- x) a second priority output for providing a second delayed priority timing signal;
- and
- j) a plurality, N-1, of multiplexers arranged between adjacent ones of the N switch element arrays, each one of the N-1 multiplexers having
- i) a mode input, coupled with the mode input of the circuit, for receiving a multicast/unicast mode signal which is a portion of the mode signal received by the mode input of the circuit,
- ii) a control input for receiving a control signal corresponding to the particular multiplexer, wherein the control signal is derived from the mode signal provided to the mode input port of the circuit,
- iii) a first address timing input for receiving a first candidate address timing signal,
- iv) a second address timing input, coupled with the second address output of a preceding switch element array, for receiving a second candidate address timing signal,
- v) a first priority input, coupled with the timing signal inputs, for receiving a first candidate priority timing signal,
- vi) a second priority input, coupled with the second priority output of the preceding switch element array, for receiving a second candidate priority timing signal,
- vii) a first group of inputs, coupled with the first group of inputs of the circuit, for receiving a first group of candidate input cells,
- viii) a second group of inputs, coupled with the first group of outputs of the preceding switch element array, for receiving a second group of candidate input cells,
- ix) a mux output, coupled with the first address timing input of a next multiplexer, for providing a mux address timing signal,
- x) an address output, coupled with the address timing input of a next switch element array, for providing an address timing signal,
- xi) a priority output, coupled with the priority timing input of the next switch element array, for providing a priority timing signal, and
- xii) a group of outputs, coupled with the first group of inputs of the next switch element array, for providing a group of output cells,
- wherein, in each circuit, the group of outputs is coupled with the second group of inputs of a lower adjacent circuit.
31 more elements
Dependencies are inferred from the claim text.