Mixed-modulo address generation using shadow segment registers

A computer-implemented method for generating a linear address in a full-width adder in a central processing unit (CPU), the linear address being a sum of a first address component and a second address component and a third address component, the first and the second address component having a reduced width less than a full width while the third address component having the full width, the first, second, and third address components each being represented by a plurality of signals on a bus, the method comprising:

• zero-extending the first address component from the reduced width to the full width by copying a zero signal to bit positions in the full width but not in the reduced width, producing an extended first address component;
• zero-extending the second address component from the reduced width to the full width by copying the zero signal to bit positions in the full width but not in the reduced width, producing an extended second address component;
• generating in the full-width adder on the CPU an initial full-width sum of the extended first address component, the extended second address component, and the third address component;
• outputting the initial full-width sum generated by the full-width adder onto a full-width bus in the CPU;
• determining in a reduced-modulus carry generator on the CPU when a partial sum of the first address component and the second address component is equal to or exceeds a reduced modulus;
• generating a reduced-modulus carry-out signal when the partial sum is equal to or exceeds a reduced modulus;
• when the carry-out is not signaled, outputting the initial full-width sum as the linear address;
• when the carry-out is signaled, recirculating the initial full-width sum to an input of the full-width adder and adding to the initial full-width sum a correction term to generate the linear address in the full-width adder in a subsequent step,
• whereby reduced-width address components are added to full-width address components in the full-width adder and the correction term is added when the carry-out is signaled by the reduced-modulus carry generator.

An address generate unit comprising:

• a four-port adder for adding four inputs together in a full modulus and outputting a sum;
• a register file for storing address components and segment bases, the register file having two ports for supplying two address components or segment bases in a cycle;
• a shadow segment register, coupled an input of the four-port adder, for storing a segment base which is also stored in the register file;
• a zero-extender, for extending address components which are reduced width to a full width of the four-port adder and inputting extended address components to the four-port adder;
• a reduced-modulus carry generator, receiving the address components which are reduced width, for generating carries beyond a reduced modulus for a partial sum of the address components received;
• a correction term generator, receiving the carries generated, for outputting a correction term to the four-port adder when at least one carry is generated;
• and
• a sum feedback path, for feeding the sum from the four-port adder to an input of the four port-adder for use in a subsequent cycle, the four-port adder adding the correction term to the sum to generate a corrected sum,
• wherein the corrected sum being the address generated when a carry is generated but the sum being the address generated when the carry is not generated.