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US 5,789,758 AGranted
Chalcogenide memory cell with a plurality of chalcogenide electrodes
AssigneeMicron Technology, Inc.
InventorAlan R. Reinberg
Life of this patent
Estimating the term…
Abstract
A chalcogenide memory cell with chalcogenide electrodes positioned on both sides of the active chalcogenide region of the memory cell. The chalcogenide memory cell includes upper and lower chalcogenide electrodes with a dielectric layer positioned therebetween. The dielectric layer includes an opening defining a pore. A volume of chalcogenide material formed integral to the upper chalcogenide electrode is contained within the pore. The upper and lower chalcogenide electrodes both have greater cross sectional areas than the pore.
Claims15
A memory cell, comprising:
- a first layer comprising phase changing material;
- a second layer comprising phase changing material;
- a dielectric layer coupled to said first and second layers, said dielectric layer including an opening defining a pore;
- and
- a volume of phase changing material contained within said pore and electrically coupled to said first and second layers, wherein a cross sectional area of said first layer and a cross sectional area of said second layer are both greater than a cross sectional area of said pore.
2 more elements
A memory cell array, comprising:
- an addressing matrix;
- and
- a plurality of memory cells operably coupled to said addressing matrix, each memory cell including:
- an upper electrode comprising phase changing material;
- a lower electrode comprising phase changing material;
- a dielectric layer positioned between said upper and lower electrodes and including an opening defining a pore;
- and
- a volume of material contained within said pore operably coupled to said upper and lower electrodes wherein a cross sectional area of said upper electrode and a cross sectional area of said lower electrode are both greater than a cross sectional area of said pore.
5 more elements
A memory cell, comprising:
- a diode assembly formed of a plurality of vertically aligned material layers within said memory cell;
- and
- a resistive assembly arranged in vertical alignment with said diode assembly, said resistive assembly in electrical communication with said diode assembly, said resistive assembly comprising:
- a lower electrode comprising phase changing material;
- a dielectric element positioned above said lower electrode;
- and
- an upper electrode comprising phase changing material positioned above said dielectric element;
- wherein said dielectric element comprises an aperture configured to restrict an area of electrical communication between said upper and lower electrodes and wherein a cross sectional area of said lower electrode and a cross sectional area of said upper electrode are both greater than a cross sectional area of said aperture.
5 more elements
Dependencies are inferred from the claim text.