Loop-back test system and method

A loop back test system for detection of intra-domain errors of an integrated I/O interface circuit core of an integrated circuit, comprising in operative combination:

• a) means for transmitting data, said transmitting means comprising:
• i) a transmitter input means for receiving input data, said input data encoded with alignment pattern, and said input data having a first format, and
• ii) a data conversion means for converting said input data from said first format into a second format;
• b) means for receiving transmitted data, said receiving means comprising:
• i) a receiver conversion means for buffered receiving transmitted output data having said second format, and converting said transmitted output data from said second format to said first format to provide received reconverted data, and,
• ii) a receiver data alignment means for extracting said encoded alignment pattern from the reconverted data, and for aligning the reconverted data to conform to timing of said transmitter input data timing;
• c) a first switching means in electrical cooperation with said data conversion means for switching converted input test data from said data conversion means to said receiver conversion means upon assertion of a loop back signal to the I/O interface circuit core, said converted input test data encoded with the alignment pattern;
• d) a second switching means in electrical cooperation with said receiver converter stage having a first open position to permit receipt of externally transmitted data, and a second closed condition for receiving an input test data for reconversion, and alignment of the reconverted input test data to provide an output test data, and for halting receipt of the externally transmitted data upon assertion of the loop back signal to the I/O interface circuit core;
• and
• e) an error analysis means for comparing said output test data with said input test data.

A loop back test method for detection of intra-domain errors of an integrated I/O interface core of an integrated circuit, comprising the following steps in any operative order:

• a) providing the integrated I/O interface core having both a transmitter section and a receiver section, said transmitter section comprising:
• i) a transmitter input stage for receiving transmitter input data, said input data encoded with an alignment patter and said input data having a first format, and
• ii) a transmitter converter stage for converting said input data into transmitter output data, said output data having a second format,
• and said receiver section comprising:
• iii) a receiver converter stage for receiving said transmitter output data for conversion of said output data to said first format to provide received reconverted data,
• iv) a receiver alignment stage for decoding said alignment pattern from said received reconverted data, and for aligning said received reconverted data to conform to timing of said transmitter input data;
• said transmitter input stage further comprising:
• v) a first switching circuit in electrical cooperation with said transmitter input stage having a first open condition, and a second closed condition, said second closed condition for shunting transmitter input test data from said transmitter converter stage to said receiver converter stage to provide loop back data to said second receiver converter stage, said first switching circuit second closed condition being enabled upon assertion of a loop back signal to the I/O interface core, and
• said receiver further comprising:
• vi) a second switching circuit in electrical cooperation with said receiver converter stage having a first open position to permit receipt of externally transmitted data, and a second closed condition for receiving said loop back data for reconversion of said loop back data to said first format to provide output test data, and for halting receipt of said externally transmitted data, said second closed condition being enabled upon assertion of the loop back signal to the I/O interface core;
• and
• an error analysis circuit for comparing said output test data with said input test data,
• b) asserting a loop back test enable signal to the I/O interface core to enable said second closed condition of said first switching circuit, and to enable said second closed condition of said second switching circuit;
• c) inputting said transmitter input data into said transmitter input stage, said input test data encoded with the alignment pattern;
• d) converting said input test data in said transmitter converter stage from the first format to the second format;
• e) shunting said input test data directly to a said receiver converter stage for conversion of said input test data from said second format to said first format;
• f) decoding said alignment pattern from said input test data for alignment of said input test data;
• g) aligning said input test data to provide aligned output test data;
• and
• h) comparing said aligned output test data with said input test data.