US 5,786,979 A · High density inter-chip connections by electromagnetic coupling

Abstract

Signal communication paths between multiple chips are established through inter-chip electro-magnetic coupling, thereby potentially eliminating mechanical inter-chip contacts and increasing inter-chip interconnection capacity while maximizing chip real estate allocated to a circuit layer. In one embodiment, multiple chips each include a conductive layer, disposed over a circuit layer on a substrate, divided into electro-magnetic coupling device elements such as capacitor plates. When utilizing capacitor plates, chips are arranged face-to-face with opposing chips having mirror image capacitor plate patterns to form a plurality of capacitors. Conventional signal transmission circuits produce time-varying signals which propagate to conventional signal receiving circuits of another chip via an embodiment of electro-magnetic signal communication paths formed by the capacitors. In another embodiment, one of the chips may function as a passive chip carrier that includes a conventional communication path between sets of capacitor plates that capacitively interconnect multiple chips that are facially opposed to the chip carrier. In another embodiment, chips having a capacitive interconnect layer can be combined into arrays with each array arranged in an offset, face-to-face spatial orientation with respect to at least one other array. Because the arrays are offset, one chip may be capacitively coupled to more than one other chip. As a result, any chip may communicate with any other chip by propagating a transmitted signal from chip to chip via capacitor links until received by a destination chip.

Claims37

Dependent claims

An assembly comprising:

a first chip having a first substrate and a first circuit disposed on a face of the first substrate, the first chip further having a first means for coupling disposed over the face of the first substrate and coupled to the first circuit;
and
a second chip, disposed in a face-to-face spatial relationship to the first chip, the second chip having a second substrate and a second circuit disposed on a face of the substrate, the second chip further having a second means for coupling disposed over the face of the second substrate and coupled to the second circuit, wherein the first and second means for coupling provide at least one electromagnetic path between the first and second chips for time-varying signals.

A chip interconnection assembly comprising:

a first chip having a first substrate layer, a first circuit on a face of the first substrate layer, a first insulation layer disposed over the face of the first substrate layer, a plurality of first conductive plates disposed on the first insulation layer, a plurality of first vias disposed through the first insulation layer and respectively coupling the first conductive plates to the first circuit, and a second insulation layer disposed over the first conductive plates;
and
a second chip having a second substrate layer, a second circuit on a face of the second substrate layer, a third insulation layer disposed over the face of the second substrate layer, a plurality of second conductive plates disposed on the third insulation layer, a plurality of second vias disposed through the third insulation layer and respectively coupling the second conductive plates to the second circuit, and a fourth insulation layer disposed over the second conductive plates;
wherein the first chip is disposed in a face-to-face spatial orientation relative to the second chip and at least one of the first conductive plates is juxtaposed with at least one of the second conductive plates to form a capacitor.

1 more element

Dependencies are inferred from the claim text.

High density inter-chip connections by electromagnetic coupling

Life of this patent

High density inter-chip connections by electromagnetic coupling

Life of this patent

Abstract

Claims37