Variable sample-rate DAC/ADC/converter system
AssigneeAnalog Devices, Inc.
InventorsRobert W. Adams, Tom W. Kwan
Life of this patent
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AssigneeAnalog Devices, Inc.
InventorsRobert W. Adams, Tom W. Kwan
Estimating the term…
A digital oversampling noise-shaping system includes a digital noise-shaped clock signal generating circuit, including a DCO operating at a fixed master clock rate, that receives a digital input sample clock signal having an input sample rate and produces a noise-shaped clock signal having a variable rate with an average rate equal to a multiple of the input sample rate. In one embodiment, an interpolator is coupled to the clock signal generating circuit and receives the digital input samples at an input sample rate and, responsive to the noise-shaped clock signal, upsamples the digital input samples at the variable rate. A hold circuit repeats the interpolated samples at the master clock rate. A digital noise-shaping circuit, coupled to the hold circuit, performs digital noise-shaping on the repeated samples received from the hold circuit. In another embodiment, a decimator is coupled to the clock signal generating circuit. Digital input samples having an input sample rate are latched to the input of the decimator at a rate controlled by the noise-shaped clock signal. The clock signal generating circuit includes a PLL in one embodiment. The digital noise-shaping circuit, in one embodiment, includes sigma-delta modulator in which the downstream one of first and second integrators operates at a reduced multiple of a fixed master clock rate.
A digital oversampling noise-shaping system comprising:
A digital oversampling noise-shaping system comprising:
A method of upsampling and noise-shaping digital input samples comprising the steps of:
A digital decimation system comprising:
Dependencies are inferred from the claim text.