Method of manufacturing high performance bipolar transistors in a BiCMOS process

A method of fabricating an emitter of a bipolar transistor in a BiCMOS integrated circuit comprising the steps of:

• forming a silicon dioxide layer over a surface of a silicon substrate;
• depositing an oxide protecting layer overlying the silicon dioxide layer;
• patterning the silicon dioxide and oxide protecting layers to furnish footings for prospectively supporting lateral edges of the emitter while leaving a medial portion of the emitter in contact with the silicon substrate;
• depositing a first layer of polysilicon film overlying the surface of the silicon substrate and the footings;
• patterning the first layer of polysilicon film to form the emitter by selectively etching the polysilicon film so that a bottom surface of the first layer of polysilicon film has a medial opening abutting the surface of the silicon substrate and lateral edges abutting the silicon dioxide layer and oxide protecting layer footings;
• removing the footings, leaving lateral notches at the bottom of the first layer of polysilicon film;
• depositing a second layer of polysilicon film overlying the surface of the first polysilicon film layer and the emitter and filling the emitter lateral notches;
• and
• etching back the second layer of polysilicon film, leaving the second layer of polysilicon film as emitter sidewalls and filling the notches of the first layer of polysilicon film.

A method of fabricating a BiCMOS integrated circuit comprising the steps of:

• forming a plurality of field oxide regions in a silicon substrate for separating a plurality of bipolar and CMOS transistor elements;
• forming a silicon dioxide layer overlying the surface of the silicon substrate and the field oxide regions;
• depositing an oxide protecting layer overlying the silicon dioxide layer;
• patterning the silicon dioxide layer and the oxide protecting layer to furnish bipolar transistor footings for prospectively bearing edges of the bipolar transistor emitter, removing the silicon dioxide layer and oxide protecting layer from the silicon substrate and field oxide film surfaces in locations other than bipolar footing locations;
• forming a gate oxide layer overlying the surface of the footings, the silicon substrate and the field oxide regions;
• depositing a first layer of polysilicon film overlying the gate oxide layer;
• patterning the gate oxide layer and the first polysilicon film to furnish CMOS footings for prospectively bearing a CMOS gate, removing the gate oxide layer and the first polysilicon film from the silicon substrate and field oxide region surfaces in locations other than CMOS footing locations;
• depositing a second layer of polysilicon film overlying the surface of the silicon substrate, field oxide regions and the bipolar and CMOS footings;
• patterning the second layer of polysilicon film to form a base electrode, an emitter electrode, a collector electrode, a gate, and CMOS source/drain openings including selectively etching the second layer of polysilicon film so that
• the bottom surface of the bipolar emitter has a medial opening abutting the surface of the silicon substrate and lateral edges abutting the bipolar and CMOS footings and
• a bottom of the CMOS gate abuts the surface of the first layer of polysilicon film;
• removing the bipolar footings, leaving lateral notches at the bottom of the bipolar emitter;
• depositing a third layer of polysilicon film overlying the surface of the second polysilicon film layer, the CMOS gate and the bipolar emitter and filling the lateral notches;
• etching back the third layer of polysilicon film, leaving the third layer of polysilicon film as bipolar emitter and CMOS gate sidewalls and filling the lateral notches of the CMOS emitter;
• and
• implanting ions in the silicon substrate.