Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array

A method for refreshing memory cells in a memory circuit comprising:

• sensing a temperature;
• generating a signal indicative of said temperature;
• varying a refresh rate of said memory cells depending upon said signal indicative of said temperature,
• accessing a ROM look-up table to determine a desired refresh rate for said temperature.

A memory circuit comprising:

• a memory array including a plurality of memory cells, wherein each of said memory cells includes:
• a storage transistor with a first terminal, a second terminal, and a gate, said first terminal coupled to a predetermined voltage;
• a read transistor coupled to said second terminal, said read transistor configured to conduct a current through said storage transistor when a read signal is asserted;
• and
• a write transistor coupled to said gate, said write transistor configured to store a charge on said gate of said storage transistor when a write signal is asserted;
• an analog-to-digital converter coupled to detect a value indicative of a voltage across said storage transistor, wherein said analog to digital converter is configured to convert said value to one of at least three distinct digital values;
• a refresh circuit coupled to said memory array and configured to refresh said plurality of memory cells;
• a temperature sensor for generating a temperature signal indicative of a temperature;
• and
• a control circuit coupled to said temperature sensor and to said refresh circuit, wherein said control circuit is configured to generate a refresh rate signal dependent upon said temperature signal generated by said temperature sensor;
• wherein said refresh circuit is configured to vary a rate of said refresh of said plurality of memory cells depending upon said refresh rate signal.