Two-device memory cell on SOI for merged logic and memory applications

A memory apparatus comprising:

• means for generating a write word signal, a read word signal and a precharge signal;
• means for generating a power voltage and a gate reference voltage;
• a first field-effect transistor having a source connected to the read word signal, a drain connected to the precharge signal, a gate connected to the gate reference voltage, and a body;
• charging means for receiving the write word signal and an externally generated write bit signal and for selectively charging and discharging the body of the first field-effect transistor between a depleted condition and a non-depleted condition representative of the externally generated write bit signal in response to the write word signal, wherein
• the gate reference voltage is set relative to a voltage of the read word signal so that, when the body of the first field effect transistor is in the non-depleted condition, the read word signal forward biases a junction between the source and the body of the first field-effect transistor in response,
• whereby said forward biasing effects a bipolar current flowing into the drain of the first field effect transistor when the first field effect transistor is in said non-depleted condition.

A digital logic and memory apparatus comprising:

• means for generating a plurality of write word signals, a plurality of read word signals, a plurality of precharge signals, and a bit;
• means for generating a power voltage and a gate reference voltage;
• an array of memory cells, each memory cell comprising:
• a first field-effect transistor having a source connected to a read word signal from said plurality of read word signals, a drain connected to a precharge signal from said plurality of precharge signals, a gate connected to the gate reference voltage, and a body;
• and
• charging means for receiving a write word signal from said plurality of write word signals and an externally generated write bit signal and for selectively charging and discharging the body of the first field-effect transistor between a depleted condition and a non-depleted condition representative of the externally generated write bit signal in response to the received write word signal, wherein
• the gate reference voltage is set relative to a voltage of the received read word signal so that, when the body of the first field effect transistor is in the non-depleted condition, the read word signal forward biases a junction between the source and the body of the first field-effect transistor in response,
• whereby said forward biasing effects a bipolar current flowing into the drain of the first field effect transistor when the first field effect transistor is in said non-depleted condition.