Structure and method for manufacturing improved FETs having T-shaped gates
AssigneeNational Science Council
InventorsHorng-Chih Lin, Tiao-Yuan Huang
Life of this patent
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Abstract
A structure and method for manufacturing improved FETs having T-shaped gates can reduce the parasitic resistance of the gate and source/drain of an FET. In the improved FETs having T-shaped gates formed according to the invention, since a buffer layer under spacers comprises a gate oxide layer and a thicker first dielectric layer, there is no stress problem as in the prior art. Furthermore, since the polysilicon gate is lower in height than the spacers, a bridge effect can be prevented. Meanwhile, since a T-shaped conductive layer is formed to increase the equivalent width of the gate, thereby avoiding the narrow line-width effect.
Claims9
A method for manufacturing improved FETs having T-shaped gates, comprising the steps of:
- providing a substrate on which a polysilicon gate, a thin oxide layer and extended source/drain regions are already formed;
- forming a first dielectric layer on said substrate;
- forming source/drain regions by use of an ion implantation process;
- forming a second dielectric layer on said first dielectric layer;
- etching said second dielectric layer to form spacers;
- etching said first dielectric layer and said thin oxide layer to expose the top of said polysilicon gate and said source/drain regions;
- and
- forming a conductive layer on the top of said polysilicon gate and said source/drain regions, wherein said conductive layer and said polysilicon gate make up a T-shaped gate conductive layer.
Dependencies are inferred from the claim text.