Dual-instruction-set architecture CPU with hidden software emulation mode

A method for processing instructions from two separate instruction sets on a central processing unit (CPU), said method comprising:

• decoding instructions from a first instruction set with a first instruction decoder, said first instruction set having a first encoding of instructions;
• decoding only a subset of instructions from a second instruction set with a second instruction decoder, said second instruction set having a second encoding of instructions, said first encoding of instructions independent from said second encoding of instructions;
• selecting said decoded instruction from either said first instruction decoder or from said second instruction decoder;
• and
• executing said decoded instruction that was selected,
• whereby instructions from both said first instruction set and said second instruction set are executed by said CPU.

A method for processing instructions from a complex instruction set computer (CISC) instruction set on a reduced instruction set computer (RISC) Central Processing Unit (CPU), said method comprising:

• attempting to decode an instruction with a CISC instruction decode unit that does not decode all instructions in said CISC instruction set;
• directly executing said instruction in an execute unit if said CISC instruction decode unit is able to decode said instruction;
• entering an emulation mode if said CISC instruction decode unit is not able to fully decode said instruction, indicating that said execute unit cannot directly execute said instruction;
• disabling said CISC instruction decode unit and enabling a RISC instruction decode unit when entering emulation mode;
• loading an instruction pointer with an address of a software emulation routine for emulating said undecodable instruction, said routine comprising instructions from a separate RISC instruction set;
• decoding RISC instructions with said RISC instruction decode unit as
• aid software routine is executed;
• executing said RISC instructions in said execute unit;
• and
• exiting emulation mode, disabling said RISC instruction decode unit and enabling said CISC instruction decode unit when said end of said software emulation routine is reached,
• whereby all instructions from said CISC instruction set are executed, either directly by said execute unit or by emulation with a software emulation routine comprised of RISC instructions.

A microprocessor for executing instructions belonging to a reduced instruction set computer (RISC) instruction set and for executing instructions belonging to a complex instruction set computer (CISC) instruction set, said microprocessor comprising:

• RISC instruction decode means, for decoding instructions belonging to said RISC instruction set;
• CISC instruction decode means, for decoding only a subset of instructions belonging to said CISC instruction set;
• mode register means for indicating a current operating mode of said microprocessor;
• enable means, coupled to said RISC instruction decode means and said CISC instruction decode means, for enabling said-decoding of instructions belonging to said RISC instruction set or belonging to said CISC instruction set, said enable means responsive to said current operating mode of said microprocessor;
• and
• an execution unit, coupled to said RISC instruction decode means and said CISC instruction decode means, for executing instructions belonging to said RISC instruction set and instructions belonging to said CISC instruction set,
• whereby instructions from said RISC instruction set and instructions from said CISC instruction set can be executed by said execution unit.