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US 5,781,031 AGranted
Programmable logic array
AssigneeInternational Business Machines Corporation
InventorsClaude Louis Bertin, John Edward Cronin
Life of this patent
Estimating the term…
Abstract
A programmable logic array (PLA) includes two direct-write EEPROM arrays, and PLA logic circuitry, such as feedback, drivers and input and output circuitry. One EEPROM array acts as an AND array and the other acts as n OR array. The PLA can be used for a memory function or a PLA function. In one aspect, the EEPROM arrays are placed on a first chip and the PLA logic circuitry a second chip. The first and second chips are stacked face-to-face, and force-responsive self-interlocking microconnectors are used to physically and electrically connect the separate chips. The separate chips are fabricated concurrently to reduce turn-around time.
Claims42
A programmable logic array (PLA), comprising:
- a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA, wherein said plurality of memory cells and memory circuits comprises:
- a first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, said first memory array acting as an AND array and said plurality of columns acting as product term lines;
- a second memory array coupled to said first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, said second memory array acting as an OR array and said plurality of columns acting as product term lines;
- PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs;
- and
- mode selection circuitry permitting operation of said plurality of memory cells as a memory apart from said PLA.
3 more elements
A programmable logic array (PLA), comprising:
- a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA, and wherein said plurality of memory cells comprises a plurality of electrically erasable read only memory (EEPROM) cells;
- and
- PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs.
A programmable logic array (PLA), comprising:
- a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA;
- and
- PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs, wherein said plurality of inputs comprises a plurality of bit partitioning input circuits.
A programmable logic array (PLA), comprising:
- a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA;
- PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs;
- and
- a plurality of drivers for driving said plurality of memory cells.
1 more element
A programmable logic array (PLA), comprising:
- a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA, wherein each of said plurality of memory cells comprises a transistor and a flip-flop controlling gate bias on said transistor;
- and
- PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs.
A programmable logic array (PLA), comprising:
- a plurality of memory cells and memory circuits, wherein said plurality of memory cells reside on a first semiconductor chip;
- and
- PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs, and wherein said PLA logic circuitry resides on a second semiconductor chip stackable with said first semiconductor chip, said PLA further comprising a plurality of connectors for connecting said first semiconductor chip and said second semiconductor chip.
A method of making a programmable logic array (PLA), comprising:
- (a) providing a first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, wherein said first memory array acts as an AND array, and wherein said plurality of columns act as product term lines;
- (b) providing a second memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, wherein said second memory array acts as an OR array, and wherein said plurality of columns act as product term lines;
- (c) programming said first memory array and said second memory array;
- (d) electrically coupling said plurality of columns of said first memory array with said plurality of columns of said second memory array;
- (e) providing PLA logic circuitry having a plurality of inputs and a plurality of outputs;
- (f) electrically coupling at least one of said plurality of outputs of said PLA logic circuitry with at least one of said plurality of inputs of said PLA logic circuitry, thereby providing at least one feedback connection;
- (g) electrically coupling at least some of said plurality of inputs of said first memory array with at least some of said plurality of inputs of said PLA logic circuitry;
- (h) electrically coupling at least some of said plurality of outputs of said second memory array with at least some of said plurality of outputs of said PLA logic circuitry;
- and
- (i) providing a plurality of memory circuits to allow operation of said first memory array and said second memory array for storage apart from said PLA.
7 more elements
A method of making a programmable logic array (PLA), comprising:
- (a) providing a first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns;
- (b) providing a second memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, wherein said steps (a) and (b) comprise providing on a first semiconductor chip;
- (c) programming said first memory array and said second memory array;
- (d) electrically coupling said plurality of columns of said first memory array with said plurality of columns of said second memory array;
- (e) providing PLA logic circuitry having a plurality of inputs and a plurality of outputs, and wherein said step (e) comprises providing on a second semiconductor chip;
- (f) electrically coupling at least one of said plurality of outputs of said PLA logic circuitry with at least one of said plurality of inputs of said PLA logic circuitry, thereby providing at least one feedback connection;
- (g) electrically coupling at least some of said plurality of inputs of said first memory array with at least some of said plurality of inputs of said PLA logic circuitry;
- and
- (h) electrically coupling at least some of said plurality of outputs of said second memory array with at least some of said plurality of outputs of said PLA logic circuitry, said method further comprising steps of:
- forming a plurality of connectors for connecting said first semiconductor chip and said second semiconductor chip;
- and
- stacking said first semiconductor chip with said second semiconductor chip, wherein said first memory array acts as an AND array, wherein said plurality of columns act as product term lines, wherein said second memory array acts as an OR array, and wherein said plurality of columns act as product term lines.
9 more elements
Dependencies are inferred from the claim text.