Low voltage EEPROM/NVRAM transistors and making method

A method for fabricating an electrically programmable memory device which has efficiency of electron injection from the channel to floating gate comprising:

• providing a semiconductor substrate having isolated surface regions therein;
• providing source and drain regions with a channel therebetween within at least one of said isolated regions;
• forming a vertical step within at least one of said isolated regions having said source and drain regions by etching into said substrate with its location between said source and drain and to a desired depth;
• implanting to form an N- region over at least said vertical step and in contact with either of said source and drain regions;
• wherein said N- drain region is formed in self-alignment with the vertical step region's edge and the depth of said N- drain region is greater than the source region;
• forming a floating gate structure over portions of said source and drain regions and said channel, which structure includes a dielectric layer and a conductor layer thereover;
• and
• said channel under said floating gate having both horizontal and vertical components.

A method for fabricating an electrically programmable memory device which has efficiency of electron injection from the channel to floating gate comprising:

• providing a semiconductor substrate having isolated surface regions therein;
• forming a word line gate structure within at least on of said regions;
• forming a source region adjacent to a word line gate structure;
• forming an N- drain region adjacent to said word line gate structure but spaced from said source region;
• forming a vertical step within at least one of said isolated regions having said N- drain region by etching into said substrate with its location between said source and drain and to a desired depth;
• implanting to form a highly doped drain region within said N- drain region and to a depth greater than said N- region;
• forming a contact to said source region to be a word line contact;
• forming a floating gate structure over portions of said source and drain regions and said channel, which structure includes a dielectric layer and a conductor layer thereover;
• and
• said channel under said floating gate having both horizontal and vertical components.

A method for fabricating an electrically programmable memory device which has greater efficiency of electron injection from the channel to the floating gate comprising:

• providing a semiconductor substrate having isolated surface regions therein;
• providing source and drain regions with a channel therebetween within at least one of said isolated regions;
• said source and drain regions are at a level below the surface of said isolated regions;
• forming a vertical step within said channel and trench at least one of said isolated regions having said source and drain regions by etching into said substrate with its location between said source and drain and to a depth of more than 300 nm,
• implanting to form an N- region over at least vertical step and in contact with said drain region;
• forming a floating gate structure over portions of said source and drain regions and said channel, which structure includes a dielectric layer and a conductor layer thereover;
• said dielectric layer is formed on said step and said trench and said conductor layer is polysilicon and is deposited over said dielectric layer within said trench and without of said trench;
• said polysilicon layer is planarized to leave only that portion of said layer that is within said trench to complete said floating gate structure;
• and
• said channel under said floating gate having both horizontal and vertical components.

A method for fabricating an electrically programmable memory device which has efficiency of electron injection from the channel to floating gate comprising:

• providing a semiconductor substrate having isolated surface regions therein;
• forming a vertical step within at least one of said isolated regions by etching into said substrate to a desired depth to form a trench;
• implanting to form a N+ region on the horizontal surface above said vertical step and a N+ region at the bottom horizontal surface within the said trench to act as source and drain regions;
• forming a floating gate structure over portions of said source and drain regions and the channel therebetween, which structure includes a dielectric layer and a conductor layer thereover;
• and
• said channel under said floating gate having both horizontal and vertical components.