Multi-threaded cell for a memory

In a multi-threaded memory formed from a plurality of multi-threaded storage cells for use in a multi-threaded computer system using plural threads with a single processor, said single processor processing one thread at a time, said processor including at least one write decoder supplying information to a selected one of the multi-threaded storage cells and at least one read decoder accessing information from a selected one of the multi-threaded storage cells, each multi-threaded storage cell including N storage elements, where N.gtoreq.2, a write interface operatively connected to said at least one write decoder, and supplying information to said plural storage elements, and a read interface operatively connected to said at least one read decoder and reading information from said plural storage elements, a method of thread selection comprising the step of:

• providing each of said N storage elements with a thread-correspondent content;
• intra-cellularly selecting one of said plurality of thread-correspondent contents based at least in part by identifying the corresponding thread;
• and
• connecting the selected one of said plurality of thread-correspondent contents to said single processor through at least one of said write and read interfaces.

In a multi-threaded computer system using plural threads with a single processor, said single processor processing one thread at a time, a multi-threaded memory comprising:

• a plurality of multi-threaded storage cells;
• at least one write decoder supplying information to a selected one of the multi-threaded storage cells;
• at least one read decoder accessing information from a selected one of the multi-threaded storage cells;
• each of the multi-threaded storage cells including:
• N storage elements, where N.gtoreq.2, each of said N storage elements having a thread-correspondent content,
• a write interface, operatively connected to said at least one write decoder, and supplying information to said plural storage elements, and
• a read interface, operatively connected to said at least one read decoder, and reading information from said plural storage elements,
• at least one of said read and write interfaces including:
• an N-selector selecting one of the N storage elements corresponding to a selected thread;
• and
• at least one port connecting the N-selector to the at least one decoder in a ratio of at least one port per decoder.

In a multi-threaded computer system using plural threads with a single processor, said single processor processing one thread at a time, a multi-threaded memory comprising:

• a plurality of multi-threaded storage cells;
• at least one write decoder supplying information to a selected one of the multi-threaded storage cells;
• at least one read decoder accessing information from a selected one of the multi-threaded storage cells;
• each of the multi-threaded storage cells including:
• N storage elements, where N.gtoreq.2, each of said N storage elements having a thread-correspondent content,
• a write interface, operatively connected to said at least one write decoder and at least on storage element, and supplying information to said plural storage elements, and
• a read interface, operatively connected to said at least one read decoder and at least one storage element, and reading information from said plural storage elements;
• the N storage elements in a multi-threaded storage cell being connected in a ring;
• a thread selection being made by shifting the thread-correspondent contents in the storage elements through the ring until the contents corresponding to a desired thread are located in the storage element to which the interface is connected.

In a multi-threaded computer system using plural threads with a single processor, said single processor selecting a cell and a thread therein to be processed and processing one thread at a time, a multi-threaded memory comprising:

• a three-dimensional array of storage elements organized as a two-dimensional array of cells, each cell having a plurality of storage elements,
• a first dimension of said array corresponding to a number of cells in said array, a second dimension corresponding to a number of bits per one of said storage elements, and a third dimension corresponding to a number of threads per one of said cells, where each one of said storage elements in a cell is operable to store a thread;
• and
• one of a first combination of a write decoder for decoding write addresses of cells in said array and a read decoder for decoding read addresses of cells in said array, a second combination of a said write decoder and at least two said read decoders, and a third combination of said read decoder and at least two said write decoders.