# US 5,777,887 A · FPGA redundancy

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- Number: US 5,777,887 A
- Document ID: US5777887A
- Status: Granted
- Kind: A
- Application number: 08/439,675
- Filed: 1995-05-12
- Granted: 1998-07-07
- Earliest claimed: 1995-05-12
- Assignees: Crosspoint Solutions, Inc.
- Inventors: David P. Marple; Laurence H. Cooke
- Web page: https://patentgrep.com/patent/US5777887A

## CPC

- H03K 19/17704: the logic functions being realised by the interconnection of rows and columns
- H03K 19/17764: for reliability
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An FPGA includes primary resources and redundant resources. To program an FPGA to perform a desired function, a pattern of programmable elements to be programmed that takes advantage of primary resources only is first prepared. This pattern is then modified responsive to previously obtained information about defects within the FPGA. The modified pattern takes advantage of redundant resources as direct or indirect substitutes for FPGA elements rendered unusable by defects. The FPGA is programmed in accordance with the modified pattern.

## Claims

### Claim 1

In an integrated circuit having an array of functional units and conducting line segments, each functional unit including a plurality of ports, said conducting line segments including line segments connected to said ports of said functional units and unconnected line segments, said line segments crossing each other in a predetermined pattern at intersections, said intersections having programmable devices connected to said crossing line segments programmable to connect said crossing line segments, said array being divided into a plurality of columns of individual functional units and surrounding programmable devices, wherein one or more of said columns are preselected to be redundant, a method of programming said integrated circuit to perform a desired function by programming selected ones of said programmable devices, said method comprising the steps of:
testing said integrated circuit to obtain column defect information identifying a defective column;
generating a first interconnection pattern of programmable devices to be programmed for said integrated circuit to perform said desired function, none of said programmable devices being included in said redundant columns;
modifying said first interconnection pattern by displacing programmable devices to be programmed in said defective column by one column toward a redundant column and displacing columns between said defective column and said redundant column by one column toward said redundant column, thereby obtaining a second interconnection pattern of programmable devices to program for said integrated circuit to perform said desired function; and
programming the programmable devices in said second interconnection pattern.

### Claim 2 (depends on 1)

The method of claim 1 wherein said functional units are MOS transistors.

### Claim 3 (depends on 1)

The method of claim 1 wherein said programmable devices are antifuses.

### Claim 4 (depends on 1)

The method of claim 1 wherein one or more of said conducting line segments include extensions, said extensions being connected to programmable devices that are unavailable for said first interconnection pattern.