Methods to enhance SOI SRAM cell stability

Abstract

Modifications of a digital logic device, such as a static or dynamic random access memory (SRAM or DRAM) or pass gate logic circuit or the like, implemented with complementary metal-oxide-semiconductor (CMOS) structures formed with silicon-on-insulator (SOI or, more specifically, SOICMOS) technology effectively suppress transient parasitic bipolar current disturbances (e.g. transient half select write disturb instabilities) caused by a discharge current through a parasitic lateral bipolar transistor formed under the transfer gate field effect transistors. Level shifting of the "off" voltage applied to the gate electrode of the transfer gate transistor dynamically changes the gain of the cell transfer gate to increase memory cell stability without compromising the memory capacity per chip or read/write memory cycle time even though level shifting can greatly increase majority carrier density in the floating body (gate) of a SOICMOS transistor at a particular level shifted voltage range. Alternatively, or additionally, the discharge of deselected cells can be slowed to avoid instability by increasing resistance of the transistors in the data buffer (with saving of chip space) and/or increasing bit line capacitance by increasing bit line length (allowing increased memory array size or an additional cell array on a chip).

Dependencies are inferred from the claim text.