Planar redistribution structure and printed wiring device

A planar redistribution structure for carrying at least one semiconductor chip and for subsequent lamination to a multilayer electronic substrate, said structure comprising

• a dielectric layer having an upper major surface and a lower major surface, said dielectric layer defining a plurality of vias communicating between said upper and lower major surfaces wherein said vias are plated-through-holes,
• a plurality of signal redistribution lines on said upper major surface for electrical connection to at least one semiconductor chip,
• a plurality of input/output pads in electrical contact with selected ones of said signal redistribution lines, said input/output pads being carried on said upper major surface and communicating with respective vias in said dielectric layer, said input/output pads and said signal redistribution lines being substantially the same height whereby the upper surfaces of said signal redistribution lines and said input/output pads are essentially coplanar and wherein said plated-through-holes are formed from a metal plated on the interior surfaces of said vias, the metal in each plated-through-hole being in electrical contact with said respective input/output pads such that the tops of said plated-through-holes are defined by said input/output pads whereby the tops of said plated-through-holes define an even topography with said redistribution lines at the upper surface of said dielectric, and
• a plurality of joining patterns on the lower major surface of said dielectric layer, said joining patterns communicating with respective vias in said dielectric layer wherein said joining patterns are larger in lateral dimension than said input/output pads.