Digital delay lock loop for clock signal frequency multiplication

A method of providing an apparatus including a digital delay lock loop for generating frequency multiples of an input clock signal, said method comprising the steps of:

• providing a programmable digital delay oscillator circuit for performing the step of receiving at least one delay control signal and a reference clock signal and in accordance therewith generating an output clock signal, wherein said reference clock signal includes a reference clock signal frequency, said output clock signal includes an output clock signal frequency, said programmable digital delay oscillator circuit includes an internal signal delay which is controlled by said at least one delay control signal and said output clock signal frequency is controlled by said internal signal delay;
• providing a phase comparison circuit, coupled to said programmable digital delay oscillator circuit, for performing the step of receiving said reference clock signal and said output clock signal and in accordance therewith generating at least one phase comparison result signal, wherein said reference clock signal further includes a reference clock signal phase, said output clock signal further includes an output clock signal phase and said at least one phase comparison result signal represents a difference between said reference clock signal phase and said output clock signal phase;
• providing a digital counter, coupled to said programmable digital delay oscillator circuit, for performing the step of receiving said reference clock signal and said output clock signal and in accordance therewith generating at least one digital count signal;
• and
• providing a delay controller, coupled to said programmable digital delay oscillator circuit, said phase comparison circuit and said digital counter, for performing the step of receiving said at least one phase comparison result signal and said at least one digital count signal and in accordance therewith generating said at least one delay control signal.

A method of generating frequency multiples of an input clock signal with a digital delay lock loop, said method comprising the steps of:

• receiving at least one delay control signal and a reference clock signal and in accordance therewith generating an output clock signal, wherein said reference clock signal includes a reference clock signal frequency, said output clock signal includes an output clock signal frequency and said output clock signal frequency is controlled by a signal delay which is controlled by said at least one delay control signal;
• receiving said reference clock signal and said output clock signal and in accordance therewith generating at least one phase comparison result signal, wherein said reference clock signal further includes a reference clock signal phase, said output clock signal further includes an output clock signal phase and said at least one phase comparison result signal represents a difference between said reference clock signal phase and said output clock signal phase;
• receiving said reference clock signal and receiving and counting said output clock signal and in accordance therewith generating at least one digital count signal;
• and
• receiving said at least one phase comparison result signal and said at least one digital count signal and in accordance therewith generating said at least one delay control signal.