Test systems for obtaining a sample-on-the-fly event trace for an integrated circuit with an integrated debug trigger apparatus and an external pulse pin

A method for collecting a continuous trace of internal test node signal events occurring on internal test nodes of an integrated circuit, comprising the steps of:

• (a) setting a delay time to an initial value;
• (b) resetting said integrated circuit to an initial state;
• (c) programming a programmed trigger event of a programmable debug trigger apparatus to a predetermined trigger capture event and a programmed time delay to said delay time, said programmable debug trigger apparatus disposed internal and integral to said integrated circuit and configured to receive a plurality of integrated circuit signals of said integrated circuit and to generate a trigger capture signal said programmed time delay after said plurality of integrated circuit signals satisfy a predetermined relationship to said programmed trigger event;
• (d) programming said internal programmable debug trigger apparatus to latch a test access port which monitors a plurality of test nodes internal to said integrated circuit upon the occurrence of said trigger capture signal and to signal an external pulse on an external pulse pin of said integrated circuit within a programmed delay after the occurrence of said trigger capture signal, wherein said programmed delay is set to said delay count;
• (e) initiating operation of said integrated circuit;
• (f) latching a plurality of test node signals present on a plurality of test nodes internal to said integrated circuit when said trigger capture signal is received;
• (g) outputting an external output signal to indicate that said plurality of test node signals have been latched;
• (h) retrieving said plurality of test node signals when said external output signal indicates that said plurality of test node signals have been latched;
• (i) determining if more trace events are needed;
• and
• (j) incrementing said delay count and repeating steps (b) through (i) if more trace events are needed.

A test system for debugging functional and electrical failures of an integrated circuit, comprising:

• a programmable debug trigger apparatus disposed internal and integral to said integrated circuit for generating a trigger capture signal a programmed time delay after a plurality of integrated circuit signals satisfy a predetermined relationship to a programmed trigger event;
• a test access port (TAP) disposed internal and integral to said integrated circuit comprising a TAP latch, said TAP latch coupled to a plurality of test nodes internal to said integrated circuit and responsive to said trigger capture signal for latching a plurality of test node signals present on said plurality of test nodes when said trigger capture signal is received;
• an external output of said integrated circuit coupled to said TAP and responsive to said trigger capture signal for outputting an external output signal to indicate that said TAP latch has been latched;
• a reset input of said integrated circuit for resetting said integrated circuit to an initial state;
• a test access port retrieval system coupled to said TAP;
• and
• a diagnostics retrieval system coupled to said integrated circuit and configured to reset said integrated circuit to said initial state, to program said programmed trigger event to a predetermined trigger capture event and said programmed time delay to a first delay value, to receive said external output signal, and to retrieve said plurality of test node signals from said TAP latch when said external output signal indicates that said TAP latch has been latched, to reset the integrated circuit again, to program said programmed trigger event to said predetermined trigger capture event and said programmed time delay to a second delay value which is incrementally greater than said first delay value, to receive said external output signal, and to retrieve said plurality of test node signals from said TAP latch when said external output signal indicates that said TAP latch has been latched;
• wherein said programmable debug trigger apparatus comprises:
• a plurality of programmable trigger registers disposed internal and integral to said integrated circuit, each trigger register configured to receive a plurality of integrated circuit signals, to compare each of said plurality of integrated circuit signals of said integrated circuit to a programmed trigger condition, and to produce a trigger match signal when said plurality of integrated circuit signals match said programmed trigger condition;
• a plurality of programmable trigger function blocks disposed internal and integral to said integrated circuit, each trigger function block coupled to receive a plurality of said trigger match signals and performing a programmed boolean minterm function on the monitored trigger match signals to produce a trigger capture signal;
• and
• a programmable timer disposed internal and integral to said integrated circuit enabled by said trigger capture signal of a first corresponding one of said programmable trigger function blocks to generate a timer enable signal upon completion of a programmed time delay.