Integrated circuit memory devices having improved dual memory bank control capability and methods of operating same

An integrated circuit memory device, comprising:

• first and second banks of memory cells;
• memory bank control means, coupled to said first and second banks of memory cells, for selectively disposing said first and second banks of memory cells in active modes of operation during respective nonoverlapping time intervals in response to first and second master clock signals having amplitudes which alternate between first and second binary logic potentials;
• strobe buffer means, responsive to a row address strobe signal having an amplitude which alternates between first and second binary logic potentials, for generating first and second control signals;
• and
• bank select buffer means, responsive to the first and second control signals and a bank select signal having an amplitude which alternates between first and second binary logic potentials, for generating the first and second master clock signals at the first binary logic potential during nonoverlapping time intervals and at the second binary logic potential during overlapping time intervals:
• wherein said strobe buffer means comprises a first NOR gate;
• and wherein said bank select buffer means comprises a second NOR gate.

A method of operating an integrated circuit memory device containing first and second banks of memory cells therein, comprising the steps of:

• generating a row address strobe signal having an amplitude which alternates between respective first and second binary logic potentials;
• generating a bank select signal having an amplitude which alternates between respective first and second binary logic potentials;
• switching the first bank of memory cells from a precharge mode of operation to an active mode of operation if the amplitude of the bank select signal is at a first logic potential upon an occurrence of a transition in the amplitude of the row address strobe signal from the first logic potential to the second logic potential;
• and
• switching the second bank of memory cells from a precharge mode of operation to an active mode of operation if the amplitude of the bank select signal is at a second logic potential upon an occurrence of a transition in the amplitude of the row address strobe signal from the first logic potential to the second logic potential.