Integrated circuit analog-to-digital converter and associated calibration method and apparatus

A analog-to-digital converter (ADC) integrated circuit comprising:

• sampling means for sampling an analog input signal;
• a first subconverter stage being connected to said sampling means and a second subconverter stage connected to said first subconverter stage, said first subconverter stage comprising a switched capacitor amplifier for driving the second subconverter stage, said switched capacitor amplifier having a non-ideal gain;
• reference voltage means for generating respective reference voltages for said first and second subconverter stages, said reference voltage means comprising
• original reference voltage output means for providing an original reference voltage to the first subconverter stage, and
• adjusted reference voltage output means for providing an adjusted reference voltage to the second subconverter stage to compensate for the non-ideal gain of said switched capacitor amplifier so that capacitor trimming for said amplifier is not needed;
• and
• output means connected to said subconverter stages for generating a digital output signal.

A analog-to-digital converter (ADC) integrated circuit comprising:

• sampling means for sampling an analog input signal;
• a subconverter stage and timing control means associated therewith for successively operating said subconverter stage a plurality of times, said subconverter stage comprising an amplifier for driving a subsequent operation of said subconverter stage, said amplifier having a non-ideal gain;
• reference voltage means for generating reference voltages for each operation of said subconverter stage, said reference voltage means comprising adjusted reference voltage output means for providing an adjusted reference voltage for a second operation of said subconverter stage to compensate for the non-ideal gain of said amplifier;
• and
• output means connected to said subconverter stage for generating a digital output signal.

A analog-to-digital converter (ADC) integrated circuit comprising:

• sampling means for sampling an analog input signal;
• a subconverter stage and timing control means for successively operating said subconverter stage a plurality of times, said subconverter stage comprising a switched capacitor amplifier for driving a subsequent operation of said subconverter stage, said switched capacitor amplifier having a non-ideal gain;
• reference voltage means for generating reference voltages for each operation of said subconverter stage, said reference voltage means comprising
• original reference voltage output means for providing an original reference voltage to a first operation of the subconverter stage, and
• adjusted reference voltage output means for providing an adjusted reference voltage for a second operation of the subconverter stage to compensate for the non-ideal gain of said switched capacitor amplifier so that capacitor trimming for said amplifier is not needed;
• and
• output means connected to said subconverter stages for generating a digital output signal.

A method for enhancing the accuracy of an analog-to-digital converter (ADC) integrated circuit of a type comprising a first subconverter stage and a second subconverter stage connected thereto, the first subconverter stage comprising an amplifier for driving the second subconverter stage, the amplifier having a non-ideal gain;

• and reference voltage means for generating reference voltages for the subconverter stages, the reference voltage means comprising adjustable reference voltage output means for providing a adjusted reference voltage to the second subconverter stage, said method comprising the steps of:
• generating a first output histogram for the ADC;
• and
• adjusting the adjustable reference voltage output means, based upon the first output histogram, to provide an adjusted reference voltage to the second subconverter stage to compensate for the non-ideal gain of the amplifier and thereby provide enhanced accuracy for the ADC integrated circuit.

A method for enhancing the accuracy of an analog-to-digital converter (ADC) integrated circuit of a type comprising a subconverter stage and timing control means for successively operating the subconverter stage a plurality of times, the subconverter stage comprising an amplifier having a non-ideal gain;

• and reference voltage means for generating reference voltages for successive operations of the subconverter stage, the reference voltage means comprising adjustable reference voltage output means for providing an adjusted reference voltage for a second operation of subconverter stage, said method comprising the steps of:
• generating a first output histogram for the ADC;
• and
• adjusting the adjustable reference voltage output means, based upon the first output histogram, to provide an adjusted reference voltage for the second operation of the subconverter stage to compensate for the non-ideal gain of the amplifier and thereby provide enhanced accuracy for the ADC integrated circuit.

An apparatus for enhancing the accuracy of an analog-to-digital converter (ADC) integrated circuit of a type comprising a first subconverter stage and a second subconverter stage connected thereto, the first subconverter stage comprising an amplifier for driving the second subconverter stage, the amplifier having a non-ideal gain;

• and reference voltage means for generating reference voltages for the subconverter stages, the reference voltage means comprising adjustable reference voltage output means for providing an adjusted reference voltage to the second subconverter stage, said apparatus comprising:
• first histogram means for generating a first output histogram for the ADC;
• and
• first adjusting means for adjusting the adjustable reference voltage output means, based upon the first output histogram, to provide an adjusted reference voltage to the second subconverter stage to compensate for the non-ideal gain of the amplifier and thereby provide enhanced accuracy for the ADC integrated circuit.

An apparatus for enhancing the accuracy of an analog-to-digital converter (ADC) integrated circuit of a type comprising a subconverter stage and timing control means for successively operating the subconverter stage a plurality of times, the subconverter stage comprising an amplifier having a non-ideal gain;

• and reference voltage means for generating reference voltages for successive operations of the subconverter stage, the reference voltage means comprising adjustable reference voltage output means for providing an adjusted reference voltage for a second operation of subconverter stage, said apparatus comprising:
• first histogram means for generating a first output histogram for the ADC;
• and
• first adjusting means for adjusting the adjustable reference voltage output means, based upon the first output histogram, to provide an adjusted reference voltage for the second operation of the subconverter stage to compensate for the non-ideal gain of the amplifier and thereby provide enhanced accuracy for the ADC integrated circuit.