Computing apparatus configured for partitioned processing

A communication processor integrated on a single substrate for performing a digital computational algorithm to generate an external signal, the algorithm including a plurality of first-type complex mathematical instructions, and a plurality of second-type non-complex mathematical instructions, the communication processor comprising:

• an analog-to-digital converter coupled to an input which receives analog input signals, the analog-to-digital converter providing digital input signals;
• a plurality of digital signal processors coupled to said analog-to-digital converter, said digital signal processors receiving said digital input signals, said digital signal processors executing said first-type mathematical instructions on said digital input signals and generating a plurality of first instruction results;
• a plurality of general purpose processors coupled to said analog-to-digital converter and said digital signal processors, said general purpose processors executing said second-type mathematical instruction on said digital input signals and said first instruction results, said general purpose processors generating second instruction results, said general purpose processors executing said second-type mathematical instructions at least partially simultaneously with said digital signal processors executing said first-type mathematical instructions;
• a digital-to-analog converter coupled to said digital signal processors and said general purpose processors, said digital-to-analog converter providing analog output signals indicative of at least one of said first instruction results and said second instruction results as said external signal;
• and
• wherein said digital signal processors effect execution of said second-type instructions by said general purpose processors wherein said digital signal processors and said general purpose processors exchange said first and second instruction results when performing said digital computational algorithm.

An apparatus for algorithmically treating received information to generate result information in response to a plurality of instructions, said plurality of instructions including a first set of complex mathematical instructions for manipulating said received information, a second set of non-complex mathematical instructions for manipulating said received information, and a third set of instructions for controlling general system operation of the apparatus, the apparatus comprising:

• a signal receiving means for receiving said received information;
• first-type processing means coupled with said signal receiving means for executing said non-complex mathematical instructions on said received information and generating first instruction results, said first-type processing means further responding to said third set of instructions to control the operation of the apparatus;
• second-type processing means, including a plurality of digital signal processors, coupled with said first-type processing means for executing said complex mathematical instructions on said received information and said first instruction results and generating second instruction results at least partially simultaneously with said first-type processing means execution of said non-complex mathematical instructions and said third set of instructions;
• an output means for outputting said result information, said output means being coupled with said first-type processing means and with said second-type processing means, said result information being related to said first instruction results or said second instruction results;
• and
• a communication means for communicatingly coupling said signal receiving means, said first-type processing means, said second-type processing means, and said output means, said communication means including a first data bus, a second data bus and a RAM controller, the RAM controller being coupled between the first data bus and the second data bus, the first data bus being coupled to the second-type processing means, the second data bus being coupled to the first-type processing means, the first and second instruction results being communicated via said first data bus, said second data bus and said RAM controller between said first-type processing means and said second-type processing means.

A method of performing a computationally intensive algorithm and a system function in a communications processor integrated on a single substrate, the algorithm including a first-type complex mathematical instruction, and a second-type non-complex mathematical instruction, the communications processor including a first digital signal processor coupled to an input, a second digital signal processor coupled to the input, a general purpose processor coupled to the input, and an output coupled to the first digital signal processor, the second digital signal processor, and the general purpose processor, the method comprising the steps of:

• receiving a first input signal at the input;
• receiving a second input signal at the input;
• executing the first-type mathematical instruction on the first input signal with the first digital signal processor to generate a first instruction result;
• executing the first-type mathematical instruction on the second input signal with the second digital signal processor to generate a second instruction result;
• receiving a third input signal at the input;
• providing a signal to the general purpose processor to cause the general purpose processor to execute the second-type mathematical instruction on the third input signal to generate a third instruction result, the general purpose processor executing at least partially simultaneously with the first digital signal processor;
• executing the first-type mathematical instruction with the first digital signal processor or the second digital signal processor on the third instruction result;
• and
• executing the second-type mathematical instruction with the general purpose processor on the first instruction result or the second instruction result.