US 5,768,575 AGranted

Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions

AssigneeAdvanced Micro Devices, Inc.

InventorsHarold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John Gregory Favor, Dale R. Greenley, Robert A. Cargnoni

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Abstract

A pipeline control system for implementing a virtual architecture having complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor. Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations. These operations, each having an associated tag, are issued to the functional units. Address processing unit computes addresses of the instructions and operands, performs segment relocation, and manages the processor's memory. Operations are executed by the units in a manner that is generally independent of operation processing by the other units. The units report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. Thus, the functional units enable multiple operations to be executed in a speculative and out-of-order manner to fully utilize the resources of the processor.

Claims19

Dependent claims

A method of operating a microprocessor to execute a binary program, said program being compatible with a CISC architecture, comprising:

decoding a first and second CISC instruction, said second CISC instruction having a program order after said first CISC instruction;
translating each of said first and second CISC instructions into at least one packet of multiple operation commands;
issuing said at least one packet to a plurality of pipelined RISC-like execution units, said units having a plurality of interacting pipelines, at least one of said pipelines having pipeline interlock logic, said execution units being capable of superscalar pipelined execution, at least two operation commands within said packet being issued in a same machine cycle;
speculatively executing a plurality of said operation commands associated with said second CISC instruction, finishing within a first machine cycle in a plurality of said execution units;
executing a plurality of said operation commands associated with said first CISC instruction, finishing within a second machine cycle in a plurality of said execution units, said second machine cycle occurring later in time than said first machine cycle;
storing system parameters on a history stack;
said system parameters resulting from said speculative executing step and said executing step for a given operation command;
associating said system parameters in said history stack with a packet that includes said given operation command;
and
selectively copying said system parameters associated with a particular packet to an architecturally visible register upon completion of all of the operation commands associated with said particular packet.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/405,272Filed 13 Mar 1995 · continuation in part
Priority: 24 Feb 1989
Granted: 16 Jun 1998
Term ends: Not estimatedThe source records don’t support an estimate.

Classification24 codes

G06F 9/34
Arrangements for executing machine instructions, e.g. instruction decode: addressing or accessing the instruction operand or the result ;…
G06F 9/30003
Arrangements for executing machine instructions, e.g. instruction decode: arrangements for executing specific machine instructions
G06F 9/30018
To perform operations on data operands: bit or string instructions
G06F 9/30038
Instructions to perform operations on packed data, e.g. vector, tile or matrix operations: using a mask

Family

Serial315,358Parent of this continuation-in-part · filed 24 Feb 1989
Serial483,223Parent of this continuation · filed 21 Feb 1990
Serial25,439Parent of this continuation-in-part · filed 3 Mar 1993
US 5,442,757 AParent of this continuation-in-part · filed 15 Aug 1995
US 5,226,126 AParent of this continuation
US 5,768,575 AThis patent

From the US filing history. Foreign family members aren’t listed.