ATM switch having N'c'n incoming lines and N'c'n outgoing lines, comprising:
- N'c' linewise switching matrices;
- and a synchronous interconnection network comprising c' groupwise synchronous switching cores each having k successive stages of groupwise elementary synchronous switches from a first stage to a last stage, N',c',n and k being integers greater than 0,
- wherein each one of the c' groupwise synchronous switching cores has N' groups of m outputs and at least N'm inputs, m being an integer such that m.gtoreq.2 and c'.ltoreq.m/n,
- wherein the inputs of each groupwise synchronous switching core receive synchronously ATM cells arriving on the N'c'n' incoming lines of the ATM switch,
- wherein each one of the N'c' linewise switching matrices has m inputs respectively connected the outputs of a respective one of the groups of m outputs of one of the c' groupwise synchronous switching cores, and n outputs linked to respective ones of the N'c'n' outgoing lines of the ATM switch,
- wherein each groupwise elementary synchronous switch has at least one and at most p groups of m inputs and at least one and at most p groups of m outputs, p being an integer such that p.gtoreq.2 and N'.ltoreq.p.sup.k,
- wherein the inputs of each of the c' groupwise synchronous switching cores consist of the inputs of the groupwise elementary synchronous switches of the first stage thereof, while the outputs of each of the c' groupwise synchronous switching cores consist of the outputs of the groupwise elementary synchronous switches of the last stage thereof,
- wherein each groupwise elementary synchronous switch comprises at least one and at most p elementary concentrators each having pm inputs and m outputs, and a plurality of filters each associated with a respective input of an elementary concentrator of said groupwise elementary synchronous switch, each filter being arranged for eliminating ATM cells not destined for an output of said elementary concentrator, the m outputs of each of said elementary concentrators constituting a respective group of m outputs of said groupwise elementary synchronous switch, and each input of said groupwise elementary synchronous switch being linked to a respective input of each one of the elementary concentrators thereof through the filter associated therewith,
- and wherein, if k>1, each one of the c' groupwise synchronous switching cores further comprises groups of m lines, each linking a respective group of m outputs of a groupwise elementary synchronous switch of a stage of said groupwise synchronous switching core other than the last stage thereof to a respective group of m inputs of a groupwise elementary synchronous switch of a next stage of said groupwise synchronous switching core.