US 5,768,193 A · Bit-refreshable method and circuit for refreshing a nonvolatile flash memory

Abstract

In a method and circuit for refreshing a flash memory with a memory array, data corresponding to that stored in a memory cell of the memory array is read by applying a read voltage thereto. Thereafter, an erase verify voltage lower than the read voltage is applied to the memory array, and conduction of the memory cell is sensed. Based on non-conduction of the memory cell and the data of the memory cell, the memory cell is selectively discharged to compensate for undesired charge gain. Subsequently, a program verify voltage higher than the read voltage is applied to the memory array, and conduction of the memory cell is sensed. Based on conduction of the memory cell and the data of the memory cell, the memory cell is selectively charged to compensate for undesired charge loss. A method and circuit for initiating the refresh operation automatically is also disclosed.

Claims19

Dependent claims

A method of refreshing a flash memory with a memory array, said method comprising the steps of:

reading data corresponding to that stored in a memory cell of the memory array by applying a read voltage thereto;
applying an erase verify voltage lower than the read voltage to the memory array;
sensing conduction of the memory cell and, based on non-conduction of the memory cell and the data of the memory cell, selectively discharging the memory cell to compensate for undesired charge gain;
applying a program verify voltage higher than the read voltage to the memory array;
and
sensing conduction of the memory cell and, based on conduction of the memory cell and the data of the memory cell, selectively charging the memory cell to compensate for undesired charge loss.

3 more elements

A method of refreshing a flash memory with a multilevel memory array, said method comprising the steps of:

reading data corresponding to that stored in a memory cell of the memory array;
generating a discharge enable signal associated with the memory cell;
generating a step count pattern which has incrementing step counts;
applying stepwise decreasing erase verify signals based on the incrementing step counts to the memory array for reading the memory cell;
comparing the data with a complement of the incrementing step counts, and resetting the discharge enable signal to a discharge inhibit signal when the data is greater than or equal to the complement of the incrementing step counts;
resetting the discharge enable signal to the discharge inhibit signal when the memory cell conducts after applying the erase verify signals corresponding to the incrementing step counts to the memory array;
and
if the discharge enable signal is still present after applying one of the erase verify signals to the memory array, discharging the memory cell so that a threshold voltage thereof becomes lower than said one of the erase verify signals to cure the memory cell of undesired charge gain.

5 more elements

A method of initiating a refresh operation in a flash memory with a memory array and a refreshing circuit, comprising the steps of:

(A) providing a non-volatile attribute memory having a first memory portion for storing a starting address, a second memory portion for storing a scanning mode bit, and a third memory portion for storing a write cycle record;
(B) during every power-on period, loading the starting address and the scanning mode bit in an address register and a scanning mode register, respectively;
and
(C) scanning the third memory portion of the attribute memory after each write cycle of the flash memory, including the sub-steps of:
(c1) loading the starting address from the address register into a scanning counter;
(c2) scanning the third memory portion of the attribute memory at an address corresponding to an address output of the scanning counter;
(c3) comparing data at scanned address of the attribute memory with the scanning mode bit;
(c4) if the data matches the scanning mode bit, and the scanned address is not a final address of the attribute memory, controlling the scanning counter to increment the address output thereof for scanning another address of the attribute memory and for comparing data at said another address with the scanning mode bit;
(c5) if the data does not match the scanning mode bit, writing at the scanned address such that the data thereat matches the scanning mode bit, and stopping the scanning of the attribute memory;
and
(c6) if the data matches the scanning mode bit, and the scanned address is a final address of the attribute memory, controlling the refreshing circuit to start the refresh operation for refreshing the memory array.

8 more elements

A refreshing circuit for refreshing a flash memory with a multi-level memory array, comprising:

a read-write controller including:
a read/write circuit having:
a master latch for latching data corresponding to that stored in a memory cell of the memory array;
and a slave latch for generating a discharge enable signal associated with the memory cell;
and
a step counter for generating a step count pattern which has incrementing step counts;
a voltage generator coupled to said step counter and the memory array, said voltage generator applying stepwise decreasing erase verify signals based on the incrementing step counts from said step counter to the memory array for reading the memory cell;
said read/write circuit further having:
a level comparator coupled to said master latch, said step counter and said slave latch, said level comparator comparing the data with a complement of the incrementing step counts, and resetting the discharge enable signal to a discharge inhibit signal when the data is greater than or equal to the complement of the incrementing step counts;
and a sense amplifier coupled to the memory array and said slave latch, said sense amplifier sensing conduction of the memory cell after said voltage generator applies the erase verify signals corresponding to the incrementing step counts to the memory array and resetting the discharge enable signal to the discharge inhibit signal when the memory cell conducts;
said read/write controller further including a detecting circuit coupled to said slave latch for detecting presence of the discharge enable signal;
and
a control circuit coupled to said master latch, said detecting circuit and said voltage generator, said control circuit controlling latching of the data by said master latch upon initiation of a refresh operation, said control circuit being controlled by said detecting circuit to control in turn said voltage generator to permit discharging of the memory cell so that a threshold voltage thereof becomes lower than one of the erase verify signals to cure the memory cell of undesired charge gain upon detection by said detecting circuit that the discharge enable signal is still present after application of said one of the erase verify signals.

10 more elements

A refreshing circuit for refreshing a flash memory with a multi-level memory array, comprising:

a read-write controller including:
a read/write circuit having:
a master latch for latching data corresponding to that stored in a memory cell of the memory array;
and a slave latch for generating a charge inhibit signal associated with the memory cell;
and
a step counter for generating a step count pattern which has decrementing step counts;
a voltage generator coupled to said step counter and the memory array, said voltage generator applying stepwise increasing program verify signals based on the decrementing step counts from said step counter to the memory array for reading the memory cell;
said read/write circuit further having:
a level comparator coupled to said master latch, said step counter and said slave latch, said level comparator comparing the data with a complement of the decrementing step counts and resetting the charge inhibit signal to a charge enable signal when the data is greater than or equal to the complement of the decrementing step counts;
and a sense amplifier coupled to the memory array and said slave latch, said sense amplifier sensing conduction of the memory cell after said voltage generator applies the program verify signals corresponding to the decrementing step counts to the memory array and resetting the charge enable signal back to the charge inhibit signal when the memory cell does not conduct;
said read/write controller further including a detecting circuit coupled to said slave latch for detecting presence of the charge enable signal;
and
a control circuit coupled to said master latch, said detecting circuit and said voltage generator, said control circuit controlling latching of the data by said master latch upon initiation of a refresh operation, said control circuit being controlled by said detecting circuit to control in turn said voltage generator to permit charging of the memory cell so that a threshold voltage thereof becomes higher than one of the program verify signals to cure the memory cell of undesired charge loss upon detection by said detecting circuit that the charge enable signal is still present after application of said one of the program verify signals.

10 more elements

An automatic circuit for initiating a refresh operation in a flash memory with a memory array and a refreshing circuit, said automatic circuit comprising:

a non-volatile attribute memory coupled to the refreshing circuit and having a first memory portion for storing a starting address, a second memory portion for storing a scanning mode bit, and a third memory portion for storing a write cycle record;
an address register coupled to the refreshing circuit and said attribute memory, the refreshing circuit loading the starting address into said address register during every power-on period;
a scanning mode register coupled to the refreshing circuit and said attribute memory, the refreshing circuit loading the starting mode bit into said scanning mode register during every power-on period;
and
a scanning counter coupled to said address register and the refreshing circuit;
the refreshing circuit loading the starting address from said address register into said scanning counter so as to scan said third memory portion of said attribute memory at an address corresponding to an address output of said scanning counter after each write cycle of the flash memory, the refreshing circuit comparing data at scanned address of said attribute memory with the scanning mode bit;
if the data matches the scanning mode bit, and the scanned address is not a final address of said attribute memory, the refreshing circuit controlling said scanning counter to increment the address output thereof for scanning another address of said attribute memory and for comparing data at said another address with the scanning mode bit;
if the data does not match the scanning mode bit, the refreshing circuit writing at the scanned address such that the data thereat matches the scanning mode bit, and stopping the scanning of said attribute memory;
and
if the data matches the scanning mode bit, and the scanned address is a final address of said attribute memory, the refreshing circuit initiating the refresh operation for refreshing the memory array.

7 more elements

Dependencies are inferred from the claim text.

Bit-refreshable method and circuit for refreshing a nonvolatile flash memory

Life of this patent

Bit-refreshable method and circuit for refreshing a nonvolatile flash memory

Life of this patent

Abstract

Claims19