Multi-state non-volatile semiconductor memory and method for driving the same

A non-volatile integrated circuit memory device comprising:

• a plurality of parallel bit lines on a substrate;
• a plurality of word lines on said substrate wherein said word lines are orthogonal to said bit lines;
• a plurality of memory cell strings on said substrate with each of said memory cell strings being connected at one end thereof to a respective one of said bit lines, wherein each of said memory cell strings includes a plurality of series-connected memory cells, wherein each of said memory cells includes a control gate coupled to a respective word line, a floating gate, and spaced apart source and drain regions, and wherein each of said memory cells can store multi-state data;
• a row decoder connected to each of said word lines wherein said row decoder drives a selected one of said word lines to a first threshold level during a first time interval of a read operation, wherein said row decoder drives said selected word line to a second threshold level during a second time interval of said read operation, wherein said row decoder drives said selected word line to a third threshold level during a third time interval of said read operation, and wherein said row decoder drives non-selected ones of said word lines to a word line pass level;
• a bit line selection circuit that connects a selected one of said bit lines to a current supply line during said read operation wherein said bit line selection circuit drives non-selected ones of said bit lines to a bit line pass level;
• a current supply which provides a current to said current supply line during said read operation;
• a first latch coupled to said current supply line through a first initialization circuit wherein said first initialization circuit initializes said first latch prior to said read operation;
• a second latch coupled to said current supply line through a second initialization circuit wherein said second initialization circuit initializes said second latch prior to said read operation;
• a first inverting circuit coupled to said first latch wherein said first inverting circuit inverts an output of said first latch responsive to a high voltage of said current supply line, a non-inverted state of said second latch and a first enable signal during one of said read operation time intervals;
• and
• a second inverting circuit coupled to said second latch wherein said second inverting circuit inverts an output of said second latch responsive to a high voltage of said current supply line, and a second enable signal during one of said read operation time intervals.