Methods for automatically pipelining loops

A method, performed by a data processing system having, a memory, of building a digital circuit representation including a pipeline in the memory from a textual description of a loop, comprising the steps of:

• identifying a loop carry dependency in said loop;
• identifying a producer operation of said loop carry dependency;
• identifying a consumer operation of said loop carry dependency;
• determining a number, n, of cycles within which said producer operation must be scheduled after said consumer operation;
• instantiating a placeholder node in said memory;
• node-locking said placeholder node so that it must be scheduled n cycles after said consumer operation;
• and
• constraining said producer operation to be scheduled before said placeholder node.

A method, performed by a data processing system having a memory, of building a digital circuit representation in said memory, said digital circuit representation including a pipeline derived from a textual description of a loop, said method comprising the steps of:

• identifying an access dependency of said loop;
• identifying a first access operation of said access dependency;
• identifying a second access operation of said access dependency;
• determining a number, n, of cycles within which said second access operation must be scheduled after said first access operation;
• instantiating a placeholder node in said memory;
• node-locking said placeholder node so that it must be scheduled n cycles after said first access operation;
• and
• constraining a scheduling order of said second access operation and said placeholder node.

A system for building, in a memory, a digital circuit representation which implements the behavior of a text description in said memory, said system having a processor coupled to a memory unit wherein said processor is programmed to perform logic processing, said system comprising:

• parsing logic for parsing said text description into a parsed text description, said text description including a loop with a delayed signal assignment having a delay value;
• translating logic for translating said parsed text description into said digital circuit representation, said digital circuit including a pipeline;
• and
• latency setting logic for setting a latency value of said pipeline to be said delay value of said delayed signal assignment.

A computer program product comprising:

• a computer usable medium having computer readable code embodied therein for building a digital circuit representation from a text description of a digital circuit, the computer program product comprising:
• computer readable program code devices configured to cause a computer to effect parsing said text description, said text description including a loop with a delayed signal assignment having a delay value;
• computer readable program code devices configured to cause a computer to effect translating said text description into said digital circuit representation including a pipeline;
• and
• computer readable program code devices configured to cause a computer to effect setting a latency of said pipeline equal to said delay value.