US 5,764,946 AGranted

Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address

AssigneeAdvanced Micro Devices, Inc.

InventorsThang M. Tran, James K. Pickett

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Abstract

A superscalar microprocessor is provided employing a way prediction unit which predicts the next fetch address as well as the way of the instruction cache that the current fetch address hits in while the instructions associated with the current fetch are being read from the instruction cache. The microprocessor may achieve high frequency operation while using an associative instruction cache. An instruction fetch can be made every clock cycle using the predicted fetch address from the way prediction unit until an incorrect next fetch address or an incorrect way is predicted. The instructions from the predicted way are provided to the instruction processing pipelines of the superscalar microprocessor each clock cycle.

Claims25

Dependent claims

A superscalar microprocessor comprising:

a branch prediction unit including:
a first input port wherein said first input port is configured to convey an input address and an update value during a first clock cycle, and wherein said update value includes an update way value;
a way prediction storage coupled to said input port including a plurality of storage locations wherein each of said plurality of storage locations is configured to store a branch prediction address and a way value, and wherein said way prediction storage further includes a mechanism to select one of said plurality of storage locations indexed by said input address;
and
an output port coupled to said way prediction storage wherein said output port conveys an output address and an output way value, wherein said branch prediction unit is configured to provide said branch prediction address from said one of said plurality of storage locations as said output address during said first clock cycle, and wherein said branch prediction unit is configured to provide said way value from said one of said plurality of storage locations as said output way value during said first clock cycle;
an instruction cache for storing previously fetched instruction blocks coupled to said branch prediction unit wherein said instruction cache comprises a plurality of blocks of memory, and wherein said instruction cache is coupled to receive said input address during said first clock cycle, and wherein said instruction cache is further coupled to receive said output way value during said first clock cycle, and wherein said instruction cache is configured to select one of said plurality of blocks of memory in response to said input address and to said output way value;
and
a fetch PC unit coupled to said instruction cache and said branch prediction unit, wherein said fetch PC unit is configured to receive said output address and to convey said output address as said input address upon said first input port during a second clock cycle succeeding said first clock cycle;
wherein each of said plurality of storage locations is further configured to store at least one additional address and a plurality of selection control bits, and wherein said plurality of selection control bits are indicative, in a first state, of a selection of said branch prediction address stored within one of said plurality of storage locations, and wherein said plurality of selection control bits are further indicative, in a second state, of a selection of said additional address stored within said one of said plurality of storage locations, and wherein said address so selected is conveyed on said output port as said output address, and wherein said address and said additional address form a group of addresses stored within one of said storage locations.

6 more elements

A superscalar microprocessor comprising:

a branch prediction unit coupled to receive a fetch address, wherein said branch prediction unit is configured to store a plurality of way predictions and a plurality of branch prediction addresses, and wherein said branch prediction unit is configured to select one of said plurality of way predictions in response to said fetch address and to concurrently select at least one of said plurality of branch prediction addresses in response to said fetch address;
and
an instruction cache coupled to said branch prediction unit, wherein said instruction cache is configured to provide said fetch address to said branch prediction unit, and wherein said instruction cache is configured to select one of a plurality of memory blocks included within said instruction cache according to an index of said fetch address and said one of said plurality of way predictions, and wherein said instruction cache is configured to subsequently provide said one of said plurality of branch prediction addresses as said fetch address;
a prefetch/predecode unit coupled to said instruction cache for prefetching and predecoding instructions from a main memory;
a plurality of reservation stations wherein each one of said plurality of reservation stations is coupled to a respective one of said plurality of decode units for storing decoded instructions until one of a plurality of functional units is available to execute said decoded instructions and said decoded instructions have been provided with their operands;
said plurality of functional units wherein each one of said plurality of functional units is coupled to a respective one of said plurality of reservation stations for executing said decoded instructions stored in said respective one of said plurality of reservation stations;
a load/store unit coupled to said plurality of functional units and said plurality of decode units 10 for executing load/store instructions;
a buffer coupled to said plurality of functional units, said load/store unit, and said plurality of decode units wherein said buffer stores speculatively executed results until said results are no longer speculative;
and
a register file coupled to said plurality of decode units and said buffer for storing the non speculative state of the register set.

7 more elements

A superscalar microprocessor comprising:

an instruction cache coupled to receive a fetch address, wherein said instruction cache is configured to store a plurality of cache lines of instruction bytes;
and
a branch prediction unit coupled to said instruction cache, wherein said branch prediction unit is coupled to receive said fetch address, and wherein said branch prediction unit includes a way prediction storage configured to store a plurality of way predictions and a plurality of branch prediction addresses, and wherein said branch prediction unit is configured to select one of said plurality of way predictions and one of said plurality of branch prediction addresses in response to said fetch address, and wherein said one of said plurality of branch prediction addresses corresponds to a first branch instruction within one of said plurality of cache lines of instruction bytes if said fetch address is a hit in said instruction cache, whereby said one of said plurality of branch prediction addresses corresponding to said first branch instruction is selected during a clock cycle in which said first branch instruction is fetched;
wherein said instruction cache selects said one of said plurality of cache lines of instruction bytes in response to said fetch address and said one of said plurality of way predictions;
a prefetch/predecode unit coupled to said instruction cache for prefetching and predecoding instructions from a main memory;
a plurality of reservation stations wherein each one of said plurality of reservation stations is coupled to a respective one of said plurality of decode units for storing decoded instructions until one of a plurality of functional units is available to execute said decoded instructions and said decoded instructions have been provided with their operands;
said plurality of functional units wherein each one of said plurality of functional units is coupled to a respective one of said plurality of reservation stations for executing said decoded instructions stored in said respective one of said plurality of reservation stations;
a load/store unit coupled to said plurality of functional units and said plurality of decode units 10 for executing load/store instructions;
a buffer coupled to said plurality of functional units, said load/store unit, and said plurality of decode units wherein said buffer stores speculatively executed results until said results are no longer speculative;
and
a register file coupled to said plurality of decode units and said buffer for storing the non speculative state of the register set.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/826,884Filed 8 Apr 1997 · continuation
Priority: 12 Apr 1995
Granted: 9 Jun 1998
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 9/3885
Concurrent instruction execution, e.g. pipeline or look ahead: using a plurality of independent parallel functional units
G06F 9/3832
Operand prefetching: value prediction for operands; operand history buffers
G06F 9/3844
Speculative instruction execution: using dynamic branch prediction, e.g. using branch history tables
G06F 12/0864
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: using…