Efficient address generation for convolutional interleaving using a minimal amount of memory
AssigneeAmati Communications Corporation
InventorPo Tong
Life of this patent
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AssigneeAmati Communications Corporation
InventorPo Tong
Estimating the term…
A convolutional interleaving process which utilizes an addressing scheme that enables the amount of memory to be used in the convolutional interleaving process to be reduced is disclosed. A stream of data is convolutionally interleaved at a designated interleaving depth and a designated interleaving block length such that a first symbol in a designated block has an associated predetermined delay and each subsequent symbol in the designated block has a delay equal to more than its predecessor symbol. A plurality of delay related arrays, as well as an initial value array, a lower limit array, and an upper limit array, are calculated in order to define interleaving orbits. The convolutional interleaving process is accomplished by a convolutional interleaver which is arranged to take an incoming stream of data and output an interleaved stream of bits which is conceptually partitioned into blocks. A convolutional deinterleaving process, which is similar to the convolutional interleaving process is also disclosed.
A method of convolutionally interleaving a stream of data, the convolutional interleaving being accomplished at a designated interleaving depth (d) and a designated interleaving block length (N), wherein a first symbol in a designated block has a predetermined delay associated therewith and each subsequent symbol in the designated block has a delay equal to (d-1) more than its predecessor symbol, the method comprising the steps of:
A method of convolutionally deinterleaving a stream of data, the convolutional interleaving being accomplished at a designated interleaving depth (d) and a designated interleaving block length (N), wherein a first symbol in a designated block has a predetermined delay associated therewith and each subsequent symbol in the designated block has a delay equal to (d-1) more than its predecessor symbol, the method comprising the steps of:
A convolutional interleaver arranged to convolutionally interleave an incoming stream of data and output an interleaved stream of bits, the stream of bits being conceptually partitioned into blocks, the interleaver comprising:
A method of convolutionally interleaving a stream of data, the convolutional interleaving being accomplished at a designated interleaving depth (d) and a designated interleaving block length (N), wherein a first symbol in a designated block has a predetermined delay associated therewith and each subsequent symbol in the designated block has a delay equal to (d-1) more than its predecessor symbol, the method comprising the steps of:
A method of convolutionally deinterleaving a stream of data, the convolutional interleaving being accomplished at a designated interleaving depth (d) and a designated interleaving block length (N), wherein a first symbol in a designated block has a predetermined delay associated therewith and each subsequent symbol in the designated block has a delay equal to (d-1) more than its predecessor symbol, the method comprising the steps of:
A convolutional interleaver arranged to convolutionally interleave an incoming stream of data and output an interleaved stream of bits, the stream of bits being conceptually partitioned into blocks, the interleaver comprising:
Dependencies are inferred from the claim text.