Pulse width modulator (PWM) system with low cost dead time distortion correction

A near-zero current detection circuit for distortion correction of an inductive load powered by a pair of transistors controlled by a first modulated signal and a second modulated signal, wherein a dead-time occurs between the first modulated signal and the second modulated signal during which neither modulated signal is asserted, comprising:

• a voltage sensor connected to the inductive load, the voltage sensor sensing a load voltage of the inductive load and producing a first value of an output signal when the load voltage is in a predetermined relation to a first predetermined value;
• a first latch receiving the output signal from the voltage sensor at an input to the first latch, the first latch being controlled by the first modulated signal;
• and
• a second latch receiving the output signal from the voltage sensor at an input to the second latch, the second latch being controlled by the second modulated signal;
• wherein a different value for the latched output signal of the first latch and the latched output signal of the second latch indicates that output current of the inductive load is within a predetermined magnitude of zero.

A data processing system for driving an inductive load powered by a pair of transistors controlled by a first pulse-width-modulated (PWM) signal and a second PWM signal, comprising:

• a voltage sensor connected to the inductive load, the voltage sensor sensing a load voltage of the inductive load and producing a first value of an output signal when the load voltage is in a first state relative to a predetermined value;
• a first latch receiving the output signal from the voltage sensor at an input to the first latch, the first latch being controlled by the first PWM signal such that the output signal is latched by an edge of the first PWM signal and output as a first latched output signal;
• a second latch receiving the output signal from the voltage sensor at an input to the second latch, the second latch being controlled by the second PWM signal such that the output signal is latched by an edge of the second PWM signal and output as a second latched output signal;
• a processor that receives the first latched output signal and the second latched output signal and generates the first PWM signal and the second PWM signal, wherein a dead-time is placed between the first PWM signal and the second PWM signal during which neither PWM signal is asserted, and wherein the processor modifies a duty-cycle of one of the first and second PWM signals and, upon the occurance of the first latched output signal being different than the second latched output signal, the processor modifies a duty-cycle of the other of the first and second PWM signals to correct for distortion in the output current of the inductive load induced by commutation of the output current during dead-time, the other of the first and second PWM signals being modified prior to the output current being equal to zero to correct for near-zero distortion of the output current.

A microcontroller for current distortion correction of an inductive load powered by a pair of transistors controlled by a first modulated signal and a second modulated signal, wherein a deadtime occurs between the first modulated signal and the second modulated signal during which neither modulated signal is asserted, comprising:

• a device that senses a load voltage of the inductive load;
• a latching device that stores a first value indicating the level of the load voltage during a first dead-time and stores a second value indicating the level of the load voltage during a second deadtime;
• and
• a controller that receives the stored values in the latching device and generates signals for correcting current distortion in response to the first value and the second value indicating selected levels.

A method of near-zero current detection for distortion correction of an inductive load powered by a pair of transistors controlled by a first pulse-width-modulated (PWM) signal and a second PWM signal, wherein a dead-time period occurs after each pulse of the first PWM signal during which neither the first nor the second PWM signals are asserted, the method comprising the steps of:

• sensing a first load voltage of the inductive load during a first dead-time period;
• sensing a second load voltage of the inductive load during a second dead-time period;
• and
• generating signals for correcting near-zero current distortion in response to the first value and the second value indicating selected levels.

A data processing system comprising:

• a central processing unit having an output terminal connected to an address bus, and a bidirectional connection to a data bus;
• a memory having an input terminal coupled to said address bus, and an output terminal coupled to said data bus, said memory including a plurality of storage locations which store a corresponding plurality of instructions which control the data processing system;
• a pulse width modulator having a first input terminal coupled to said address bus, a second input terminal coupled to said data bus, and an output terminal for providing at least first and second control signals;
• said first and second control signals adapted to be coupled to an inverter which drives an input of a motor;
• and
• a low current condition circuit having an input terminal adapted to receive a voltage signal which indicates a voltage at the input of the motor, and having an address input terminal coupled to said address bus, and a data output terminal coupled to said data bus for providing a low current condition signal in response to said voltage signal.