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US 5,763,922 AGranted
CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers
AssigneeIntel Corporation
InventorRobert S. Chau
Life of this patent
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Abstract
A CMOS integrated circuit having a PMOS and NMOS device with different gate dielectric layers. According to the present invention, an NMOS transistor is formed on a p-type conductivity region of a semiconductor substrate. The NMOS transistor has first gate dielectric layer formed on the p-type conductivity region. A PMOS transistor is formed on a n-type conductivity region of the semiconductor substrate. The PMOS transistor has a second gate dielectric layer wherein the second gate dielectric layer has a different composition than the first gate dielectric layer.
Claims21
A CMOS integrated circuit comprising:
- a NMOS transistor formed on a p-type conductivity region of a substrate, said NMOS transistor having a first gate dielectric layer formed on said p-type conductivity region, said NMOS transistor having a gate electrode formed on said first gate dielectric and wherein said gate electrode is coupled to either Vcc or Vss;
- and
- a PMOS transistor formed on a n-type conductivity region of said semiconductor substrate, said PMOS transistor having a second gate dielectric layer wherein said second gate dielectric layer has a different composition than said first gate dielectric layer, said PMOS transistor having a gate electrode formed on said second gate electrode and wherein said gate electrode is coupled to either Vcc or Vss.
An integrated circuit comprising:
- a NMOS transistor formed on a p2-type conductivity region of a substrate, said NMOS transistor having a first gate dielectric layer formed on said p2-type conductivity region;
- a PMOS transistor formed on a n-type conductivity region of said semiconductor substrate, said PMOS transistor having a second gate dielectric layer wherein said second gate dielectric layer has a different composition than said first gate dielectric layer;
- and
- wherein said first gate dielectric layer is nitrogen rich at the gate dielectric/substrate interface and wherein said second gate dielectric layer is less nitrogen rich at the gate dielectric/substrate interface than said first gate dielectric layer.
1 more element
An integrated circuit comprising:
- a NMOS transistor formed on a p-type conductivity region of a substrate, said NMOS transistor having a first gate dielectric layer formed on said p-type conductivity region;
- a PMOS transistor formed on a n-type conductivity region of said semiconductor substrate, said PMOS transistor having a second gate dielectric layer wherein said second gate dielectric layer has a different composition than said first gate dielectric layer;
- wherein said first dielectric layer comprises a silicon nitride layer formed on said p-type conductivity region and a silicon dioxide layer formed on said silicon nitride layer;
- and
- wherein said second dielectric layer comprises a silicon dioxide layer formed on said n-type conductivity region and a silicon nitride layer formed on said silicon dioxide layer.
2 more elements
An integrated circuit comprising:
- a NMOS transistor formed on a p-type conductivity region of a substrate, said NMOS transistor having a first gate dielectric layer formed on said p-type conductivity region;
- a PMOS transistor formed on a n-type conductivity region of said semiconductor substrate, said PMOS transistor having a second gate dielectric layer wherein said second gate dielectric layer has a different composition than said first gate dielectric layer;
- wherein said first gate dielectric layer comprises:
- a first dielectric layer formed on said p-type conductivity region and a second dielectric layer formed on said first dielectric layer wherein said second dielectric layer is different than said first dielectric layer;
- and
- wherein said second gate dielectric layer comprises said second dielectric layer formed on said n-type conductivity region and said first dielectric layer formed on said second dielectric layer.
3 more elements
An integrated circuit comprising:
- a NMOS transistor formed on a p-type conductivity region of a substrate, said NMOS transistor having a first gate dielectric layer formed on said p-type conductivity region;
- a PMOS transistor formed on a n-type conductivity region of said semiconductor substrate, said PMOS transistor having a second gate dielectric layer wherein said second gate dielectric layer has a different composition than said first gate dielectric layer:
- and
- wherein said first gate dielectric layer comprises an oxide with between 0.10-5.0 atomic percent of nitrogen confined within the bottom 5-10.ANG. of said first gate dielectric.
1 more element
An integrated circuit comprising:
- a NMOS transistor formed on a p-type conductivity region of a substrate, said NMOS transistor having a first gate dielectric layer formed on said p-type conductivity region:
- a PMOS transistor formed on a n-type conductivity region of said semiconductor substrate, said PMOS transistor having a second gate dielectric layer wherein said second gate dielectric layer has a different composition than said first gate dielectric layer:
- and
- wherein said second gate dielectric layer comprises an oxide with between 0.10-5.0 atomic percent of nitrogen confined within the top 10.ANG. of said oxide.
1 more element
An integrated circuit comprising:
- a NMOS transistor formed on a p-type conductivity region of a substrate, said NMOS transistor having a first gate dielectric layer formed on said p-type conductivity region;
- said NMOS transistor having a gate electrode formed on said first gate dielectric and wherein said gate electrode is coupled to either Vcc or Vss:
- a PMOS transistor formed on a n-type conductivity region of said semiconductor substrate, said PMOS transistor having a second gate dielectric layer wherein said second gate dielectric layer has different dielectric properties than said first gate dielectric layer;
- and
- said PMOS transistor having a gate electrode formed on said second gate electrode and wherein said gate electrode is coupled to either Vcc or Vss.
2 more elements
An integrated circuit comprising:
- a NMOS transistor formed on a p-type conductivity region of a substrate, said NMOS transistor having a first gate dielectric layer formed on said p-type conductivity region said first gate dielectric layer having a thickness between 20-50.ANG.;
- and
- a PMOS transistor formed on a n-type conductivity region of said semiconductor substrate, said PMOS transistor having a second gate dielectric layer wherein said second gate dielectric layer has a thickness between 20-50.ANG. and has different dielectric properties than said first gate dielectric layer.
Dependencies are inferred from the claim text.