Bit error measurement system

A bit error measurement system characterized in having that:

• a wide band pattern generation circuit for sequentially multiplexing parallel patterns generated by a pattern generator circuit (113) to form a high speed pattern, said wide band pattern generation circuit having an approach detection circuit (131), a clock switch circuit (128), an intermediate retiming circuit (127) and a clock edge switch circuit which cancels delay times (.tau..sub.0 +.tau..sub.1 +,,+.tau..sub.m-1) in said intermediate retiming circuit;
• and
• a clock frequency difference detector (150) provided in said wide band pattern generation circuit for counting a frequency of an input clock (111) to detect whether the counted frequency exceeds a predetermined difference from the frequency at a previous phase switching to determine either permit or prohibit a phase switch operation in said clock switch circuit (128).

A bit error measurement system having a reference pattern generator (262), a comparator (265), a pattern synchronization part (266) and an error counter (270) for measuring bit errors of a signal (261) under test characterized in that:

• said bit error measurement system has a pattern position recording part which stores address information of said reference pattern generator (262) in memory means when receiving an error detection signal (265.sub.a) from said comparator (265).

A bit error measurement system having a reference pattern generator (262), a comparator (265), a pattern synchronization part (266) and an error counter (270) for measuring bit errors of a signal (261) under test for every N bit parallel characterized in that:

• said bit error measurement system has a pattern position recording part which stores address information of said reference pattern generator (262) when receiving an error signal in any one of N bit error detection signals (265.sub.a) from said comparator (265) and said N bit error detection signals (265.sub.a) in memory means.