US 5,758,056 A · Memory system having defective address identification and replacement

Abstract

The present invention is embodied in a memory system which restores full functionality to a dynamic random access main memory having at least one defective bit. In a preferred embodiment of the invention, the memory system is integrated on an industry standard memory module which is plugged into a host computer system. The memory module incorporates a block of DRAM main memory, an SRAM replacement memory, a non-volatile memory which stores a map of defective memory locations within the main memory, and a process control module (PCM) operable in multiple modes, which manages a defective address identification and replacement process. The PCM, which contains high-speed registers, in addition to decoding and control logic, is implemented as a high-speed application-specific integrated circuit (ASIC). The PCM, which is coupled to both the host system memory address and data buses, recognizes addresses of defective memory locations within the main memory block and, in response to such recognition, suppresses output from the main memory block and provides a replacement address within the high-speed SRAM memory. The data stored at the replacement address is output to the system data bus. The process operates with sufficient speed to ensure that there is no degradation in main memory access time. The non-volatile memory can be updated by the host system to correct newly discovered defects in the main memory without removing the memory module from the system.

Claims44

Dependent claims

In combination with a host computer system having a central processing unit (CPU) coupled to both a system data bus and a linear address bus, a system memory address bus, and a memory management unit (MMU) which generates multiplexed main memory addresses which are transmitted on the system memory address bus in response to linear memory addresses received from the CPU over the linear address bus, a memory module comprising:

(a) a main memory coupled to both the system data bus and the system memory address bus, said main memory constructed from at least one row and column addressable semiconductor memory device;
(b) a replacement memory coupled to the system data bus, said replacement memory having address inputs, said replacement memory constructed from at least one semiconductor memory chip;
and
(c) a process control module (PCM) coupled to the system data bus, to the system memory address bus, and to the replacement memory address inputs, said PCM having a plurality of content addressable registers (CARs) into which defective main memory addresses and failure mode data related to each such defective address are loaded, said PCM receiving a multiplexed address from the MMU, said PCM comparing the received address with defective main memory addresses stored within the CARs, said PCM either permitting normal system access to said main memory if the received address does not match one of the loaded defective addresses or, if said received address does match one of the loaded defective addresses, said PCM deselecting the main memory and generating a replacement memory address which is transmitted to the replacement memory address inputs, said replacement memory responding by loading data stored at the received replacement memory address on the system data bus.

1 more element

A memory system for use in conjunction with a host computer system having a central processing unit (CPU) operatively coupled to both a system data bus and to a system memory address bus, said memory system comprising:

(a) a main memory operatively coupled to both the system memory address bus and the system data bus, said main memory constructed from at least one row-and-column-addressable random access memory device;
(b) a replacement memory operatively coupled to the system data bus, said replacement memory having address inputs, said replacement memory constructed from at least one semiconductor random access memory device;
and
(c) a process control module (PCM) operatively coupled to the system memory address bus, to the system data bus, and to the replacement memory address inputs, said PCM having a plurality of content addressable registers (CARs) into which defective addresses within the main memory and failure mode data related to each defective address are loaded, said PCM receiving from the system address bus a main memory address which it compares to defective main memory addresses stored within the CARs, said PCM either permitting normal system access to said main memory if the received address does not match one of the loaded defective addresses or, if said received address does match one of the loaded defective addresses, said PCM deselecting the main memory and generating a replacement memory address which is transmitted to the address inputs of the replacement memory, said replacement memory responding by transmitting data stored at the replacement memory address to the system data bus.

1 more element

Dependencies are inferred from the claim text.

Memory system having defective address identification and replacement

Life of this patent

Memory system having defective address identification and replacement

Life of this patent

Abstract

Claims44