High speed self-adjusting clock recovery circuit with frequency detection

A method of recovering a clock signal from an NRZ data bit stream comprising the steps of:

• detecting edge transitions of said NRZ data bit stream;
• generating a quadrature sample signal corresponding to said NRZ data bit stream;
• selectively passing said quadrature sample signal to a phase detector output, said quadrature sample signal being passed to said phase detector output if said NRZ data makes a low to high transition, a negative of said quadrature sample signal being passed to said phase detector output if said NRZ data signal makes a high to low transition, otherwise if said NRZ data signal makes no transition, holding a previous phase error value in said phase detector output;
• controlling a variably controlled oscillator (VCO) according to said phase detector output;
• and
• generating a recaptured clock signal by said controlled VCO, whereby said clock signal is recovered in a self-adjusting circuit with no steady state phase error, whereby ripple induced phase jitter is substantially eliminated, whereby phase error output is independent of data density and high speed operation is enabled.

A circuit for recapturing a clock signal from an NRZ data bit stream comprising:

• clocked sample and hold circuit means for sampling and holding an in-phase sample signal of said NRZ data bit stream;
• clocked sample and hold circuit means for sampling and holding-a quadrature sample signal of said NRZ data bit stream;
• phase detector circuit means for selectively passing said quadrature sample signal to a phase detector output, said quadrature sample signal being passed to said phase detector output if said NRZ data makes a low to high transition, the negative of said quadrature sample signal being passed to said phase detector output if said NRZ data makes a high to low transition, and previously passed quadrature sample signal being held at said phase detector output if said NRZ data makes no transition;
• and
• variable controlled oscillator means for receiving said phase detector output and responsively generating an in-phase clock signal, said clocked sample and hold circuit means for sampling and holding an in-phase sample signal of said NRZ data bit stream and said clocked sample and hold circuit means for sampling and holding a quadrature sample signal of said NRZ data bit stream being complementarily clocked by said inphase clock signal.