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AssigneeSamsung Electronics Co., Ltd.
InventorHwan-Ho Seong
Estimating the term…
A power factor correction circuit includes a boost converter, a zero-current detector for detecting a period in which an inductor current is zero, a half-wave rectifier for supplying a power voltage proportional to an output voltage of the boost converter, a control voltage generator for generating a control voltage to control the turn-on time timing of a sense-FET, a turn-on controller for making constant a turn-on duration of the sense-FET, an over current detector for generating a signal when a mirror terminal current of the sense-FET is greater than a predetermined current, an OR gate for performing a logic OR operation of the output signals of the turn-on controller and the over current detector, an output current controller for generating a gate drive signal of the sense-FET, and an under voltage lock out for turning off the power voltage when the power voltage is less than a predetermined voltage. This circuit enables an external pin count to be reduced by having a built-in boost converter controller and a built-in sense-FET in a single package.
A power factor correction circuit comprising:
An integrated circuit for use with a boost converter of a power factor correction circuit, comprising:
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
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Term ended 26 Dec 2016 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to a power factor correction circuit, and more particularly, to a 5-pin power factor correction circuit which is designed to reduce an external pin count by incorporating a built-in boost converter controller and a built-in sense-field effect transistor(sense-FET) in a single package.
2. Description of the Prior Art
FIG. 1 is an application circuit diagram illustrating one embodiment of a conventional power factor correction circuit;
FIG. 2 is an application circuit diagram illustrating another embodiment of a conventional power factor correction circuit;
FIG. 3 is a detailed circuit diagram of a 5-pin power factor correction circuit in accordance with a preferred embodiment of the present invention;
A preferred embodiment of the present invention is described below with reference to the accompanying drawings.
As shown in FIG. 3, the power factor correction circuit includes a boost converter 100 for controlling an input current at the boundary of a continuous and a discontinuous current after receiving a DC source from a bridge rectifier 10, the boost converter 100 including capacitors Cf, Co, an inductor Lf, a sense-FET 110 and a diode D2; a zero-current detector 200 for detecting a period in which the inductor Lf current is zero; a half-wave rectifier 300 for supplying a power voltage Vcc which is proportional to an output voltage Vo of the boost converter 100 by rectifying the inductor winding W.sub.FB voltage which in turn is proportional to an output voltage Vo when the sense-FET 110 is turned off, the half-wave rectifier 300 including a diode D1 and a smoothing capacitor Cvcc; a control voltage generator 400 for generating a control voltage Vcon to control a turn-on time of the sense-FET 110 by comparing an input voltage Vcc with a first reference voltage Vrefl after receiving the input voltage Vcc; a turn-on controller 500 for making constant the turn-on time of the sense-FET 110 by comparing a generated saw tooth wave VRAmp with the control voltage Vcon, the saw tooth wave VRAmp having a constant rise time between a start control signal START and a stop control signal STOP; an overcurrent detector 600 for generating a signal when a mirror terminal current Isense of the sense-FET 110 exceeds a predetermined current; an OR gate 700 for performing a logic OR operation upon received output signals of the turn-on controller 500 and the overcurrent detector 600; an output current controller 800 for generating a gate drive signal of the sense-FET 110 upon receiving the output signal of the zero-current detector 200 as a set S input and receiving the output signal of the OR gate 700 as a reset R input; and an under voltage lock out 900 for turning off the power voltage Vcc when the power voltage Vcc is less than a predetermined voltage.
As shown in FIG. 3, the zero-current detector 200 includes a resistor R.sub.ZCD for resistively detecting a period in which the inductor Lf current is zero, and an inverter ZCD for generating a signal when a current through the resistor R.sub.ZCD is zero.