US 5,754,878 A · CPU with DSP function preprocessor having pattern recognition detector that uses table for translating instruction sequences intended to perform DSP function into DSP macros

Abstract

A CPU or microprocessor which includes a general purpose CPU, such as an X86 core, and a DSP. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. The function preprocessor includes a pattern recognition detector which stores instruction sequences which implement DSP functions. The pattern recognition detector compares each pattern with an instruction sequence and determines if one of the patterns substantially matches the instruction sequence. If the DSP function preprocessor determines that a DSP function is being executed, the preprocessor converts or maps the opcodes to a DSP macro instruction that is provided to the DSP. The DSP executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. Thus, the DSP offloads these mathematical functions from the X86 core, thereby increasing system performance. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSPs. Thus the present invention is backwards compatible with existing software.

Claims18

Dependent claims

A central processing unit which performs digital signal processing functions, comprising:

an instruction memory for storing a plurality of instructions, wherein said instruction memory stores one or more sequences of instructions which implement a digital signal processing function;
a function preprocessor coupled to the instruction memory, wherein the function preprocessor includes:
a pattern recognition detector which stores a plurality of patterns indicative of instruction sequences which implement digital signal processing functions, wherein said pattern recognition detector examines a sequence of instructions stored in said instruction memory and compares said sequence of instructions with said plurality of stored patterns, wherein said pattern recognition detector determines whether said sequence of instructions in said instruction memory substantially matches said plurality of stored patterns, wherein a substantial match indicates that said sequence of instructions implements a digital signal processing function;
means for converting a sequence of instructions in said instruction memory which substantially matches one of said plurality of stored patterns into a digital signal processing function identifier;
one or more general purpose execution units coupled to the function preprocessor for executing instructions in said instruction memory;
one or more digital signal processing execution units coupled to the function preprocessor for performing digital signal processing functions, wherein the one or more digital signal processing execution units receive said digital signal processing function identifier and perform a digital signal processing function in response to said received digital signal processing function identifier from said function preprocessor.

3 more elements

A method for executing instructions in a central processing unit (CPU), wherein the CPU includes one or more general purpose execution units and one or more digital signal processing execution units, wherein the CPU further includes a pattern recognition detector which stores a plurality of patterns indicative of instruction sequences which implement digital signal processing functions, the method comprising:

storing a plurality of instructions in an instruction memory, where said plurality of instructions include one or more sequences of instructions which implement a digital signal processing function;
the pattern recognition detector comparing a sequence of instructions stored in said instruction memory with said plurality of stored patterns;
the pattern recognition detector determining whether said sequence of instructions in said instruction memory substantially matches one of said plurality of stored patterns, wherein a substantial match indicates that said sequence of instructions implements a digital signal processing function;
converting a sequence of said instructions in said instruction memory which substantially matches one of said plurality of stored patterns into a digital signal processing function identifier;
transferring said digital signal processing function identifier to the one or more digital signal processing execution units;
the one or more digital signal processing execution units receiving said digital signal processing function identifier;
and
the one or more digital signal processing execution units performing a digital signal processing function in response to said received digital signal processing function identifier.

5 more elements

Dependencies are inferred from the claim text.

CPU with DSP function preprocessor having pattern recognition detector that uses table for translating instruction sequences intended to perform DSP function into DSP macros

Life of this patent

CPU with DSP function preprocessor having pattern recognition detector that uses table for translating instruction sequences intended to perform DSP function into DSP macros

Life of this patent

Abstract

Claims18